SLYS035A September 2022 – September 2023 TMAG5173-Q1
PRODUCTION DATA
Figure 7-7 shows an example of standard I2C two byte write command supported by TMAG5173-Q1. The starting byte contains 7-bit secondary device address and a '0' at the R/W command bit. The MSB of the second byte contains the conversion trigger bit. Writing '1' at this trigger bit will start a new conversion after the register address decoding is completed. The 7 LSB bits of the second byte contains the starting register address for the write command. After the two command bytes, the primary device starts to send the data to be written at the corresponding register address. Each successive write byte will send the data for the successive register address in the secondary device.