SLYT835 March 2023

3 Active clamp leg design considerations

With the active snubber implemented in a PSFB, the transformer winding current will no longer rise monotonically during the effective duty cycle (D_eff) period (T_S) (non-zero output winding voltage period) like output inductor current. This is because the active snubber capacitor energy also participates in energizing output inductor rather than solely rely on energy transfer from the input side. The non-monotonic current ramp characteristic could make peak current mode control difficult as input or transformer winding current are generally utilized for peak current detection and higher input or transformer winding current does not necessarily represent larger duty cycle.

In order to allow peak current detection happens when current is rising monotonically, we must ensure D_effT_S is always greater than the duration where current-second balance is completed – D_CSBT_S – under whole operational voltage and load ranges. As high efficiency is expected for a PSFB with larger D_eff, PSFB is generally designed to have larger D_eff at mid-to-heavy load where D_eff >> D_CSB is expected. At light load, converter is expected to operate under discontinuous conduction mode where D_eff will be smaller than D_eff under continuous conduction mode at the same input/output voltage condition. In order to keep D_effT_S greater than D_CSBT_S even at light load, we have implemented frequency reduction control based on load current.

The duration of D_CSBT_S becomes an important factor for peak current mode control. How long does it take to complete current-second balance is now the one-million-dollar question. To answer this question, you’ll need to calculate current flow through the active clamp leg.

Assuming that V_CL is a constant and L_m = ∞, Equation 2 expresses the rectifier current changing rate during the duty-cycle loss period (the period where V_SEC = 0 and i_SR1 and i_SR2 are commuting) as:

Equation 2.

\frac{{∆ i}_{S R}}{∆ t} = \frac{N_{p}}{N_{S}} \frac{V_{L r}}{L_{r}} = \frac{\frac{N_{S}}{N_{P}} V_{I N} - V_{C L}}{{(\frac{N_{S}}{N_{P}})}^{2} L_{r}}

where V_Lr is the voltage across L_r.

Equation 3 calculates the changing rate of the output inductor current:

Equation 3.

\frac{{∆ i}_{L O}}{∆ t} = \frac{V_{C L} - {V O U T}_{}}{L_{o}}

Using Equation 2 and Equation 3 along with Kirchhoff’s current law, Equation 4 calculates the changing rate of the active clamp current:

Equation 4.

{∆ i}_{C L} = {∆ i}_{S R} - {∆ i}_{L o} = [\frac{\frac{N_{S}}{N_{P}} V_{I N} - V_{C L}}{({\frac{N_{S}}{N_{P}}}^{2}) L_{r}} - \frac{V_{C L} - V_{O U T}}{L_{O}}] ∆ t

Since V_CL ≈ V_IN x N_S/N_P [3], you just need to apply the total active clamp leg conduction time as Δt in Equation 4 to solve Δi_CL. However, you still need to know the peak value of i_CL in order to calculate the i_CL root-mean-square (RMS) value. As shown in Figure 3-1, if i_SEC = i_Lo (after charging C_oss to V_CL) at time t₂ and i_SEC = i_SR at time t₃ (start to charge C_CL), Equation 5 derives i_CL,peak as:

Equation 5.

i_{C L, p e a k} = {∆ i}_{C L | t 3 - t 2} = i_{C L | t 3} = (i_{S R} - i_{L O}) |t 3 - (i_{S R} - i_{L O})| t 3 = i_{S E C | t 3} - i_{S R | t 2} = {∆ i}_{S E C | t 3 - t 2} - {2 i}_{S R S | t 2} \approx - {2 i}_{S R S | t 2}

Figure 3-1 Key waveforms around the active clamp current conduction period.

With Equation 6 deriving the i_SR2 value at t₂ as:

Equation 6.

i_{S R 2 | t 2} = \frac{V_{I N}}{{}_{N_{P}}^{N_{S}}{L_{r}}} - (t_{2} - t_{1})

Assuming that the i_SR2 current decreasing rate from t₀ to t₂ is the same, Equation 7 derives the time duration of t₂-t₁ as:

Equation 7.

(t_{2} - t_{1}) = \sqrt{2 C_{O S S} \frac{N_{S} V_{C L} L_{r}}{N_{P} V_{I N}}}

Since C_Lneeds to maintain a current second balance, the sum of areas A1 and A3 will equal area A2.

As shown in Equation 7, SR C_oss controls the peak current on the active clamp leg. If you select a low C_oss SR FET, the active clamp leg RMS current is lower and thus helps improve converter efficiency.

Here are some design guidelines when designing a PSFB converter with an active snubber:

QCL must turn on only after the duty-cycle loss duration in order to avoid CCL energy backflow to the primary side.
QCL must be turn on while the body diode is still conducting current for ZVS.
A longer QCL on time will reduce VCL as well as SR voltage stress, but the QCL RMS current will increase.
A lower SR Coss will not only help reduce the active clamp leg RMS current, but also help reduce SR voltage stress.

The active clamp method isn’t limited to full-bridge rectifiers; it is applicable to other types of rectifiers such as current-doubler [4] or center-taped rectifiers. Figure 3-2 shows a PSFB converter with an active clamp on a center-taped rectifier, which is implemented in the 3-kW Phase-Shifted Full Bridge with Active Clamp Reference Design with >270-W/in³ Power Density.

Figure 3-2 A PSFB converter with active snubbers on a center-taped rectifier.

As shown in Figure 3-3, it is possible to clamp SR voltage stress under 40 V with dual active clamp legs, with negligible clamping loss (very minor conduction loss) at a 250-A load current.

Figure 3-3 Steady-state waveform of a PSFB converter with a center-taped rectifier and active snubbers at a 12-V/3-kW output.