Advanced processors and system-on-chip (SoC) with integrated point-to-point serial communication or an analog front end (AFE) require a power supply with low output-voltage ripple to maintain signal integrity and improve performance. The output-voltage ripple requirement of the processor’s point-of-load (POL) power supply can be below 2-mV, which is about one-tenth of the ripple for a typical design, putting heavy design constraint on the synchronous buck converter. Since the processor’s output current requirements exceed the capabilities of a linear post-regulator, employing a second-stage filter, a higher switching frequency and additional output capacitance greatly reduce the POL’s ripple. Synchronous-buck converters are available with several different control architectures, each having a unique method to ensure stability when designing for low-ripple voltage. This article compares three different control architectures: externally-compensated voltage-mode, constant on-time and selectable-compensation current-mode to achieve 1-mV output voltage ripple complete with test data using the same electrical specifications and comparison of output voltage ripple, solution size, load transients and efficiency.

Three different power supplies were designed and built to demonstrate the performance of each control mode under similar operating conditions. For each design, the input voltage is 12 V, the output voltage is 1 V and the output current for each device is capable of 15-A. These requirements are typical for powering a high-performance SoC that integrates sensitive analog circuitry, requiring low output voltage ripple.

To bound the filter design and performance expectations, the allowable ripple voltage is ±0.15 percent, or ±1.5 mV (3 mVpp) of the output voltage. Our comparison features three TI DC/DC converters: a 15-A D-CAP3™ buck converter (TPS548A28), a 20-A internally compensated advanced current-mode (ACM) buck converter (TPS543B22) and a 15-A voltage-mode buck converter (TPS56121). We selected output voltage, output current and operating frequencies as close as possible to one another within the converter’s capability to support similar second-stage filter components.

Even with low equivalent series resistance (ESR) ceramic output capacitors, it is not practical to use a buck converter’s inductor and capacitor (LC) output filter to achieve low output voltage ripple. Designers will likely need to use a second-stage LC filter in order to achieve output ripple below 5-mV. For more information about the design of a second-stage filter or the ripple measuring techniques, please see resources section. The value of the inductor of the second-stage filter can be calculated using Equation 1 and solving for L2. The inductor L2 is the second-stage inductor, C1 is the primary-stage output capacitor of the buck converter, and C2 is the second-stage capacitor network. For all three designs, the same second-stage filter was used (as shown in Table 3-1), occupying a circuit board area of 92mm² (as shown in Figure 3-1).

Once the second-stage inductor value (L2) is chosen and the components are assembled, the next step is to re-compensate the DC/DC converter’s control loop with the addition of the second-stage inductance and capacitance to ensure stability. It is important to mention that each control architecture has its own unique technique to re-compensate the control loop after adding the second stage filter, if needed. The output voltage ripple, efficiency penalty and stability of each control architecture were evaluated and then summarized the results.

Pulse-width modulation (PWM) with voltage-mode control architecture is accomplished by comparing a voltage error signal from the output voltage and reference voltage to a constant sawtooth-ramp waveform. The ramp is initiated by a clock signal from an oscillator. The TPS56121 employs externally-compensated, type-3 compensation addressing a double-pole power stage that allows the converter to be re-compensated after the addition of a second-stage filter. Adjusting external resistor and capacitor values after the addition of a second stage filter ensures stability. The output voltage peak-to-peak ripple without an additional filter is 4.8-mV. With the additional filter applied, the output voltage ripple is 1.9-mV (as shown in Figure 4-1). In this case, the TPS56121 design required no loop compensation adjustments to ensure stability. Figure 4-2 shows a load transient waveform with a 10-A load-step, and the output voltage waveform after the implementation of the second-stage filter shows no sign of instability.

D-CAP3 uses a one-shot timer to generate an on-time pulse that is proportional to the input voltage and the output voltage. When the falling feedback voltage equals the reference voltage, a new PWM on-pulse is generated. The ramp is emulated by the output inductor. A signal from an internal ripple-injection circuit is fed directly into the comparator with its offset voltage eliminated, reducing the need for output voltage ripple from the capacitor’s ESR. One advantage of D-CAP3 and other constant on-time converters is additional loop compensation circuitry is not required. But, the control loop may have the ability adjusted by an adjustable ramp, if the device supports this feature, and the addition of feed forward capacitance at the output voltage feedback resistor divider network. The TPS548A28 output voltage peak-to-peak ripple without an additional filter is 7.6-mV. With the additional filter applied, the output voltage ripple is 2.3-mV (as shown in Figure 5-1). In this case, the TPS548A28 design required no adjustments to ensure stability. Figure 5-2 shows a load transient waveform with the same 10-A load-step as the previous converter, and the output voltage waveform after the implementation of the second-stage filter shows no sign of instability.

Internally-compensated ACM is a ripple-based, peak-current-mode control scheme that uses an internally generated ramp to represent the inductor current. This control mode provides a balance between the faster transient response of non-linear control modes, like D-CAP3, and the broad capacitor stability of other externally-compensated, fixed-frequency control architectures, like voltage-mode control. ACM is a newer control architecture that allows the loop to be compensated with a single resistor instead of a resistor and capacitor network. The TPS543B22 has three selectable PWM ramp options to optimize the control loop performance when a second stage filter is implemented. Interestingly, we noticed that its evaluation module has capacitor and inductor solder pads on the circuit board to conveniently accommodate second-stage filter components. The TPS543B22 output voltage peak-to-peak ripple without an additional filter is 7.4-mV. With the additional filter applied, the output voltage ripple is 1.3-mV (as shown in Figure 6-1). The TPS543B22 design required no adjustments to the ramp to ensure stability. Figure 6-2 shows a load transient waveform with the same 10-A load-step as the previous converter, and the output voltage waveform after the implementation of the second-stage filter shows no sign of instability.

The full-load efficiency of each DC/DC converter was measured with and without the additional second-stage filter to compare the power losses. The results are shown in Table 7-1. The second-stage filter contributes negligible power loss and efficiency penalty. The deficiency and power loss differences were measured because each DC/DC converter has unique power MOSFETs, which lead to an inaccurate efficiency conclusion. It is the designer’s decision to determine if the efficiency penalty and additional required board space of 92mm² is worth the output voltage ripple improvement.

Designers have traditionally used an additional low drop-out (LDO) regulator to post-regulate the output voltage of a DC/DC converter and achieve low output voltage ripple. If a designer prefers to use anLDO instead of a second-stage filter, the 4-A TPS7A54 can be paralleled to provide up to 8-A. For example, if the LDO has a 175-mV voltage drop, two LDOs will dissipate 1.4-W at 8-A versus 0.02-W of the second-stage filter. The LDO will have a lower output voltage ripple noise of 4 µV, but

if the second-stage filter provides acceptable low output voltage ripple for the SoC and AFE, the advantages are a smaller design, less power loss and lower component cost.