SLYT837 January   2023 TPS543B22 , TPS548A28 , TPS56121

 

  1. 1 Introduction
  2. 2 Selecting and bounding the application
  3. 3 Designing the second-stage filter
  4. 4 Voltage-mode control architecture
  5. 5 D-CAP3 control architecture
  6. 6 Advanced current mode (ACM) control architecture
  7. 7 Efficiency penalty
  8. 8 Conclusion
  9. 9 References
  10. 10Related Websites

7 Efficiency penalty

The full-load efficiency of each DC/DC converter was measured with and without the additional second-stage filter to compare the power losses. The results are shown in Table 7-1. The second-stage filter contributes negligible power loss and efficiency penalty. The deficiency and power loss differences were measured because each DC/DC converter has unique power MOSFETs, which lead to an inaccurate efficiency conclusion. It is the designer’s decision to determine if the efficiency penalty and additional required board space of 92mm2 is worth the output voltage ripple improvement.

Designers have traditionally used an additional low drop-out (LDO) regulator to post-regulate the output voltage of a DC/DC converter and achieve low output voltage ripple. If a designer prefers to use anLDO instead of a second-stage filter, the 4-A TPS7A54 can be paralleled to provide up to 8-A. For example, if the LDO has a 175-mV voltage drop, two LDOs will dissipate 1.4-W at 8-A versus 0.02-W of the second-stage filter. The LDO will have a lower output voltage ripple noise of 4 µV, but

if the second-stage filter provides acceptable low output voltage ripple for the SoC and AFE, the advantages are a smaller design, less power loss and lower component cost.

Table 7-1 Efficiency and power loss comparison.
P/N Iout (A) Filter Efficiency Power Loss (W)
TPS543B22 15 Primary 86.43% 2.358
Primary + Secondary 86.33% 2.378
Difference -0.1% -0.02
TPS548A28 15 Primary 83.98% 2.829
Primary + Secondary 83.87% 2.850
Difference -0.11% -0.021
TPS56121 15 Primary 89.19% 1.834
Primary + Secondary 89.34% 1.806
Difference -0.15% -0.028