5 Results

Figure 5 illustrates the performance of the two-phase iTCM totem-pole PFC with the aforementioned algorithm during an AC dropout and restore event. The AC input voltage is 230 V_RMS at 60 Hz and the output voltage is 400 V. The load is 5 kW (400 V, 12.5 A) of constant current with a 20-ms AC dropout event. In order to produce the worst-case stress for the system, AC was removed such that it would return at the peak of the AC line cycle. This is the worst case for inrush current, in that the input bypass diodes will cause significant inrush current into the output capacitors when the AC line peak exceeds V_OUT.

The waveform in Figure 5 also provides an image zoomed in on the recovery portion of the event. It is clearly visible that the PFC switch current is well controlled and below the GaN FET OCP limit [12]. Minimized reverse current prevents unnecessary discharge of V_OUT. In addition, there is no abnormal behavior from the bypass diode conduction intervals, since the algorithm is able to easily determine whether the input voltage is above or equal to the output voltage.

In addition to AC dropout, the design also delivers low THD, high efficiency, high power density and fast load transient response.

If you are interested in more details on this algorithm or other aspects of this design, you can find the full schematics, layout, bill of materials, test results and code for the two-phase totem-pole PFC reference design in reference [10].