3 Techniques to minimize EMI

Several common PCB design techniques minimize EMI, also detailed in references [1], [10], [11]:

• Proper grounding. This is one of the most effective ways to reduce radiated emissions. Careful grounding can avoid ground loops that can act as antennas. Using a ground plane can also help reduce loop areas and provide a return path for signals, reducing the potential for EMI. In other cases, however, ground planes can create antennas on sensitive nodes and increase radiated emissions (see specific example shown in Figure 5).
• Component placement. Place components in a way that minimizes the length of signal traces, particularly for high-speed signals. Keep digital and analog components separate to avoid interference.
• Straight, short trace routing. Routing high-speed traces in a straight line and keeping them as short as possible can minimize the potential for EMI. Also, take care to avoid creating right angles in your trace routes, which can cause reflections and signal losses.
• Using decoupling capacitors. Decoupling capacitors can provide a short return path for high-frequency noise to ground. Place decoupling capacitors as close as possible to the power pins of ICs.
• Controlled impedance. Controlling the impedance of signal traces will match the impedance of the source and load and can help prevent signal reflections that can lead to radiated emissions.
• Shielding. Sometimes, using metal shields or shielding material on certain areas of the PCB can prevent radiated emissions.
• Using filters. Filters can block out certain frequencies that are causing radiated emissions, and are particularly useful in power-supply circuits.
• Layer stacking. In multilayer PCBs, take care to arrange the layers in a way that minimizes EMI. It’s generally good practice to alternate between power and ground layers, as this can help reduce loop areas and provide a return path for signals. Top and bottom ground layers can help act as a shield field for internal signal layers such as clocks that generate radiated emissions.
• Avoid clock harmonics. Clock signals can generate harmonics that can interfere with other parts of the circuit. Spread-spectrum techniques can help spread these harmonics out and reduce their impact.
• EMI simulations. Radiated emissions simulation tools can help predict and minimize EMI in the PCB design phase itself [12], [13].

Figure 3 is a detailed schematic of the analog signal chain introduced in Figure 2.

Figure 4 and Figure 5 illustrate the application of radiated emissions reduction techniques to the corresponding PCB layout for the AMC131M03. Figure 4 shows a “good” layout, keeping traces short for ADC inputs and power routes in the high-voltage domain (PCB area to the left of the AMC131M03 placement) and placing bypass capacitors C1, C6, C8, C9, C11, C13, C14 and C24 close to the IC.

An important aspect when mitigating EMI is the grounding scheme of the isolated ground node ISO_GND. Minimizing trace lengths and not placing a ground plane in the high-voltage domain minimizes the antenna on this node, and thus minimize radiated emissions [14]. Ferrite beads F1 and F2 are inserted into power connections DCDC_OUT and DCDC_HGND to block out high-frequency noise. You can also place an additional ferrite bead (F3) with high impedance at the frequency of excessive radiated emissions (which will depend on the PCB design) in series with the resistive divider for the voltage measurement.

Figure 5 illustrates a “bad” layout, showing a ground plane connected to the ISO_GND node, which acts as an antenna and can increase radiated emissions significantly [14].

Figure 6 and Figure 7 show the radiated emissions measurement for the AMC131M03 PCB using the layout implementation depicted in Figure 4. The measurements follow CISPR 11 requirements in a semianechoic chamber using a broadband antenna configured for horizontal and vertical polarizations with a 3m distance. The ADC is receiving a continuous clock at the CLKIN pin and is generating conversion results. However, there is no Serial Peripheral Interface communication while the emission profile is characterized. This design meets CISPR 11 Class A and Class B standards with 13dB of margin, offering the lowest radiated emissions performance on the market for an ADC with reinforced isolation for both data and power.