SNAA345 December 2020 LMK5C33216
A PLL that is locked to an input clock must be able to tolerate the wander defined in figure 5 in the G.8262 specification. The definition of tolerance is such that the device will not trigger any alarms while locked to such an input clock and it will be able to pull-in to such as an input clock. Test signals with a sinusoidal phase variation can be used, according to the levels in Table 4-1 (Table 9 in the G.8262 specification), to check conformance to the mask in figure 5 in the G.8262 specification.
Test signals with sinusoidal phase variation according to levels shown in Table 4-1 were introduced using the Calnex Paragon-T box. There were no amplitude, frequency, or missing clock cycle alarms flagged by the LMK5C33216 DUT (10-Hz loop bandwidth). The device stayed locked and was able to pull-in to the input clock throughout the duration of this test. The LMK5C33216 showed a passing result for the wander tolerance G.8262 Option 1 specification.
PEAK-TO-PEAK WANDER AMPLITUDE | WANDER FREQUENCY | ||||||
---|---|---|---|---|---|---|---|
A1 (µs) | A2 (µs) | A3 (µs) | f4 (mHz) | f3 (mHz) | f2 (mHz) | f1 (Hz) | f0 (Hz) |
0.25 | 2 | 5 | 0.32 | 0.8 | 16 | 0.13 | 10 |