The ADC128S102QML-SP may display sparkle codes at the output of the device at an infrequent rate. A sparkle code is an erroneous output code that has a predictable output value and will only appear under specific input conditions. A more complete definition and description of a sparkle code is provided in this document. This application report provides background on the sparkle code behavior and provides empirical data across various device configurations and temperatures. From the data, it was found that a sparkle code occurrence is in the order of parts-per-billion over process and temperature. Also, the ADC128S102QML-SP design differs from the catalog version of the device and these design differences make the ADC128S102QML-SP susceptible to sparkle codes, whereas the catalog version of the device is not susceptible to sparkle codes.
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The ADC128S102QML-SP may exhibit code errors called sparkle codes at the output of the device. A sparkle code is an erroneous output that occurs very infrequently under very specific input conditions. A code error is defined as an error in the output code of an analog to digital converter (ADC) that exceeds a defined error threshold. The acceptable range of an ADCs output is commonly defined to include performance parameters including, but not limited to, offset, gain, and noise. If the output exceeds the expected amplitude of the ADC’s acceptable error threshold, this is considered an error code. A sparkle code is a single erroneous output code either above or below the threshold that can be easily identified in the presence of noise, in the case of the ADC128S102-SP, by a minimum delta of 0xFF from the expected output code. Another way to explain this definition is that the observed error amplitude occurs with a probability exceeding the expected probability of the error amplitude given the ADC’s assumed Gaussian distributed noise. That is, sparkle codes are clearly visible and easily recognizable in data sample sets and data sample plots as shown in Figure 1-1.
An important characteristic that defines sparkle code is that it will only occur when the expected converter output code is at very specific values. The erroneous sparkle code measured will occur at predicted values, available in Table 3-1. For example, if the expected output code is in the range of 0x0FF – 0x100 than a sparkle could occur where the output value is 0x1FF. A sparkle code can only occur under certain output value conditions and has a predictable sparkle code value. The physical mechanism causing the sparkle code will be described in the Root Cause Analysis section.
To understand the occurrence of the sparkle code, empirical data was collected across multiple devices and multiple configurations, using a test solution that maintains the precise input conditions required to elicit sparkle codes. A detailed evaluation of the results is available further in this document, and a high-level overview of the results is provided in this section.
The custom test solution was created for this project, the hardware was defined to be able to drive the input of the ADC, and use a socket to easily change devices. The most sophisticated aspect of the test solution is the closed servo loop controlling the input voltage to the device. This provided the precise input needed to maintain the input at the necessary voltage for the converter output code to be within half an LSB of the required code transition for multiple hours to allow monitoring for sparkle codes. Details on the test solution used is found later in this document.
A frequency of sparkle code occurrence has been observed to be in the order of parts per billion (ppb) across all configurations and temperatures. At ambient room temperature the highest frequency of sparkles occurred at a clock rate of 2MSPS (125kSPS) at 2.17 sparkle codes per billion conversions. The high and low temperature range are set by the specified minimum and maximum temperature range for the device. At high temperature (125°C) the maximum sparkle rate occurred at 0.329 ppb at VA set to 5 V. At low temperature (-55°C) the maximum sparkle rate occurred at 13.318 ppb at VA set to 5 V. These results are detailed later in this document, and are aligned with design expectations.
Different device configurations were also examined for sparkle code variations. One such configuration is continuous conversion mode, where the CS signal is held low throughout conversions instead of changing state. This configuration did not show any different frequency of sparkle occurrence than previously observed. The effect of multiplexing inputs was also considered, and also showed no variation from the expected. Through all data collection, the sparkle value has been fixed for the respective code transition being observed. No sparkle codes were observed to happen consecutively.
The ADC128S102-SP was released in 2008, with over a decade in the industry. It has a long flight history with numerous successful missions and is the most used ADC in the industry to date. The device has been used across multiple applications and a sparkle code has not been observed during normal operation; it has only been observed in rigorous test conditions. Even then, it is an extremely uncommon occurrence with a very precise controlled input condition, resulting in billions of conversions within that stringent set up for a sparkle code to occur. It is also important to note that since the device’s release, there have not been any changes to fabrication or test procedures of the device.
Although a sparkle code is a rare occurrence, it is a real possibility, and mitigation methods can be put in place to protect the system. Sparkle code occurrences resemble single event transient (SET) signatures, which will be safeguarded for applications with existing mitigation methods. This can result in minimum to no modifications in existing firmware. There are various simple mitigation methods that can be implemented depending on the application. Various methods to mitigate the error will be presented in this document. A best two of three approach is explained in this document and a pseudo code created by Texas Instruments is available in section Software Example.
A multi-step ADC architecture, such as a successive approximation register (SAR) ADC, converts a continuous analog input voltage to a set of digital bits through a binary search. The binary search utilizes a high-speed decision loop to determine each bit value. The binary search starts by setting the most significant bit and comparing this value with the input voltage to determine the correct value and then setting the next significant bit. It repeats this decision loop, bit-by-bit, to build the remaining bits of the converted result. This process can introduce a sparkle code in the ADC128S102QML-SP due to the logic in the ADC having insufficient settling time. The design of the ADC128S102QML-SP is susceptible to sparkle codes due to the meta-stability of the bit-decision flip-flops used to determine the output conversion result.
A simplified block diagram is shown in Figure 3-1. The time margin for settling the flip-flops on the ADC128S102QML-SP decreased from the commercial version of the device due to the added circuitry required for radiation hardening. Note that these design differences make the ADC128S102QML-SP susceptible to sparkle codes, whereas the catalog version of the device is not susceptible to sparkle codes. It is also possible that sparkle code occurrence may be exacerbated at higher power supplies and lower temperatures as in these fast corner conditions there is less margin. Due to the nature of a sparkle code lot to lot variation cannot be bounded, and should be expected to vary as any other parametric would.
The source of a sparkle code occurrence is inherent to the digital circuitry of the ADC, and depends on the output code transition the ADC is measuring. A sparkle code may occur if the input voltage results in any lower subset of the digital code to toggle near a boundary where the most significant bit (MSB) of that subset is 0 and least significant bits (LSB) are all 1, or vice versa, where the most significant bit is 1 and the least significant bits are all 0. The output states described can be clearly seen in Table 3-1, which lists the ADC output code transitions and the respective possible sparkle value at that code transition. To further explain, a sparkle code is possible when the input voltage is at a binary multiple of the analog power supply, which acts as the reference voltage for this device. As an example, when the full-scale range is 5 V, the voltage step size is 1.2207 mV, which is equivalent to a least significant bit (LSB) and a single code increment. Therefore, an input voltage between 2.5 V and 2.49938 V (2.5 – 1 LSB) is now between the code transition 0×800 and 0×7FF. This will cause the ADC to naturally toggle between code and code ̶ 1 with equal probability based on quantization noise.
When the device is in this condition, a sparkle code is possible. Note that to achieve this condition, the input needs to have low noise and be equally within the code transition. If there is any noise, drift, or other sources of error, the output measurement could shift outside the code transition. If this occurs a sparkle code is no longer possible.
Each code transition will only sparkle to the respective listed sparkle value, no other value. The smallest sparkle delta as shown is 0×FF. The input voltage needs to be within half an LSB of this code transition for the device to output a sparkle code.
Vin/Vref Ratio | Code Transition | Sparkle Code |
---|---|---|
1/16 | 0×0FF - 0×100 | 0×1FF |
2/16 | 0×1FF - 0×200 | 0×3FF |
3/16 | 0×2FF - 0×300 | 0×200 |
4/16 | 0×3FF - 0×400 | 0×7FF |
5/16 | 0×4FF - 0×500 | 0×5FF |
6/16 | 0×5FF - 0×600 | 0×400 |
7/16 | 0×6FF - 0×700 | 0×600 |
8/16 | 0×7FF - 0×800 | 0×FFF |
9/16 | 0×8FF - 0×900 | 0×9FF |
10/16 | 0×9FF - 0×A00 | 0×BFF |
11/16 | 0×AFF - 0×B00 | 0×A00 |
12/16 | 0×BFF - 0×C00 | 0×800 |
13/16 | 0×CFF - 0×D00 | 0×DFF |
14/16 | 0×DFF - 0×E00 | 0×C00 |
15/16 | 0×EFF - 0×F00 | 0×E00 |