SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support

For networks with full timing support, the PTP stack on both Leader and Follower node devices are set to follow the default values of the PTP telecom profile G.8275.1:

  • PTP domain number is 24.
  • PTP event (Sync, Delay Request, Delay Respond) message rate is 16 packets per second.
  • Announce message rate is 8 packets per second.
  • Announce timeout is 3 missing messages.
  • Ethernet address type is Multicast.
  • Communication protocol is Layer 2.

The syn1588® PTP is configured as follows:

  • The PI control loop parameters are set to fast mode, which is a setting optimized for minimal packet delay variation (PDV).
  • The sample rate converter filter is activated
  • The non-linear spike-prefilter is activated using the default windows size of 4 seconds
  • The servo adjust rate is set to 1Hz