SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

2 syn1588® Synchronization Algorithm

The syn1588® PTP Stack waits for PTP messages from a PTP Grandmaster after performing basic initialization tasks, such as initializing the network synchronizer. When the bidirectional time transfer is established, the PTP Stack calculates the offset of the local clock with respect to the leading clock. For larger initial offsets exceeding a user-definable boundary, the PTP stack adjusts the hardware ToD clock asynchronously, by directly updating the time information. The PTP stack then calculates and adjusts the frequency offset of the local oscillator using a series of SYNC messages. Subsequently, the PTP stack corrects the residual frequency offset. The final two steps of the adjustment process are done synchronously using a dedicated hardware module of the IP core. As a result, the PTP Stack is able to adjust the clock of the PTP Follower to less than 20ns prior to engaging the PTP control servo loop.