SNAA365
June 2024
LMK5B33216
1
Abstract
Trademarks
1
Hardware Architecture
1.1
Clocking Scheme
1.2
FPGA Design
2
syn1588® Synchronization Algorithm
2.1
PTP Time-of-Day Clock Adjustment Algorithm
3
Test Setup
3.1
FMC Adapter Board
3.2
Compliance Test Setup
3.3
Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
3.3.1
Transfer Characteristic
3.3.2
Absolute Time Error
3.3.3
Lock Time
3.4
Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
3.5
Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
4
PTP System Application
5
Additional Development
6
Conclusion
7
References
7
References
Texas Instruments,
LMK5C33216A Product Folder
Texas Instruments,
LMK5C33216AS1 Product Folder
International Telecommunication Union (ITU),
G.8275.1 : Precision time protocol telecom profile for phase/time synchronization with full timing support from the network
International Telecommunication Union (ITU),
G.8275.2 : Precision time protocol telecom profile for time/phase synchronization with partial timing support from the network
terasIC,
Arria® 10 Han Pilot Platform
Texas Instruments,
TICS Pro Software
International Telecommunication Union (ITU),
G.8273.2 : Timing characteristics of telecom boundary clocks and telecom time slave clocks for use with full timing support from the network