SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

Abstract

This application note describes the performance tests and measurement results to verify the compliance of the TI network synchronizer devices (LMK5CXXXXXA, LMK5BXXXXX, and LMK5XXXXXXS1) in combination with the Oregano Systems syn1588® technology Precision Time Protocol (PTP) telecommunication profiles G.8275.1 and G.8275.2, respectively. The G.8275.1 profile covers networks with full timing support, in which all network devices provide either the PTP Boundary Clock or PTP Transparent Clock support with sufficient accuracy. Meanwhile, the G.8275.2 profile defines the PTP for networks with partial timing support, in which only some of the network devices require the PTP support. The LMK5xxxxxS1 is used for adjusting the frequency of the PTP hardware Time-of-Day (ToD) clock and is in compliance with the telecommunication accuracies of Class A (100ns), Class B (70ns), Class C (30ns), and even Class D.