SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

6 Conclusion

The combination of the syn1588® on the Arria® 10 with the LMK5XXXXXS1 is compliant with the telecommunication accuracies of Class A (100ns), Class B (70ns), Class C (30ns), and even Class D (5ns). The 1PPS signal does not deviate more than 2ns. A high-grade local oscillator offering a short-term stability of less than 1ns over 5s is mandatory to reach Class D. Additionally, all measurements are made using a direct connection between two PTP device rather than connecting one or more Boundary Clocks or Transparent Clocks.

For networks with partial timing support, the configuration of the PTP stack is optimized to handle PDVs in excess of 230µs while staying within the requested boundaries of ±1.5µs with a headroom of 500ns.