SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

1 Hardware Architecture

The software is setup using the syn1588® PTP technology, which is ported onto an Intel® Arria® 10 SoC FPGA (10AS066K3F40E2SG). The commercially available HAN Pilot Platform, offered by terasIC, is selected to minimize the overall design effort for this project. The block diagram of the complete FPGA and clocking for a single 10G Ethernet port is shown in Figure 1-1. For the 10G Ethernet interface port, the respective hard IP cores (PMA, PCS) are configured accordingly. A MAC IP core developed by Oregano Systems is connected to the 32-bit wide XGMII interface. The PTP IP core contains the PTP ToD clock along with a set of packet scanning engines that search for PTP event messages. To account for different network communication protocols (Layer 2, IPv4, IPv6 VLAN, and so forth), the scanning engines are user-configurable with the respective pattern and mask RAM blocks. All units and modules are connected through an AXI bus interface to the embedded ARM CPU.

System Block Diagram of Arria® 10 FPGA and Clocking With the syn1588® IP Core and MACFigure 1-1 System Block Diagram of Arria® 10 FPGA and Clocking With the syn1588® IP Core and MAC

After porting the Oregano syn1588® technology onto the Arria® 10 FPGA, both the hardware and software of the syn1588® technology are enhanced to use the digitally tunable network synchronizer (LMK5XXXXXS1). A standard SPI port provided by the Arria® 10 SoC FPGA is used to establish a bidirectional communication with the LMK5XXXXXS1 for configuration, status monitoring, and phase and frequency tuning through the digitally-controlled oscillator (DCO).