SNAA365 June 2024 LMK5B33216
The syn1588® IP core is easily ported to the FPGA device using a standard software tool chain. The timing report of the compiled design shows that the internal syn1588® ToD clock can operate at a system frequency of up to 250MHz. The 125MHz is chosen for the first implementation because this frequency is a common use case for ToD implementations. The 125MHz network timing PTP clock can be increased to 250MHz by reducing the output divider setting by 2 in the LMK5XXXXXS1 or doubling the 125MHz clock through an internal PLL in the Arria® 10 FPGA. Increasing the frequency to 250MHz improves the resolution of the PTP clock and the time stamp resolution without introducing any noticeable jitter.
The following list, taken from the FPGA fitter report, shows resource utilization of the FPGA design with two 10G Ethernet ports with full PTP support. For this implementation, a second pair of PCS PMA modules is instantiated with an XMAC IP core attached. While the second 10G Ethernet port requires an independent pair of packet scanning engines, the Ethernet port shares the syn1588® hardware ToD clock, which is extended with two additional time stamp registers.