SNAA366 October   2022 LMX1204

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Basic Clock Distribution System
    2. 1.2 Pre-multiplier Stage
  4. 2Low-Frequency Reference
    1. 2.1 Pre-multiplier Stage
    2. 2.2 LMX1204 Multiplier Stage
    3. 2.3 LMX1204 Multiplier vs RF Synthesizer
  5. 3Real-World Application With AFE7950 RF Sampling Transceiver
    1. 3.1 AFE7950 Clocking Measurement Setup
    2. 3.2 AFE7950 Clocking Measurement Results
  6. 4Conclusion

1 Introduction

A large phased-array radar or communication system requires many channels. Components like the AFE7950 (4T6R RF sampling transceiver), the ADC12DJ5200RF (Dual, 5.2 GSPS ADC), or the ADC32RF54 (Quad, 3 GSPS ADC) are examples of data converter devices used in such systems. The devices operate at high sampling rates and integrate multiple channels per device. An entire phased-array system employs many of the devices to satisfy the total number of channels required. Each device requires a high-quality, low phase-noise clock source. Using a low phase-noise RF synthesizer at each device for the clock is possible, but that approach is cumbersome, expensive, and DC power-prohibitive for large systems. An alternative is to use a single low phase-noise source and distribute that source to all of the required devices.

The LMX1204 is a high-frequency clock distribution chip. The device distributes a low phase-noise clock signal to multiple data converters used in large array systems. Each LMX1204 distributes the input clock to four output clocks. Designers can cascade multiple devices to scale the outputs to the required number of channels. The LMX1204 provides a straight buffer option and a divider output option. There is also an integrated multiplier. The multiplier output frequency of operation is limited between 3.2 GHz and 6.4 GHz. Multiply-by-2, 3, and 4 options are available..

As an example, consider the AFE7950 RF sampling integrated transceiver device with an input clock of around 6 GHz. The digital-to-analog converter (DAC) samples at 6 GSPS and the analog-to-digital converter (ADC) divides that clock in half (internally) to sample at around 3 GSPS. The 6-GHz clock must be distributed to each device and the proper phase matching between channels must be verified. One option is to generate the clock with an RF synthesizer like the LMX2820. That clock output is distributed to the required number of elements through the LMX1204 operating in straight buffer mode.

This note investigates an alternative approach to distribute the sample clock by taking advantage of the multiplier option in the LMX1204. The approach uses a very low phase-noise reference source oscillator which is multiplied up to the desired sample clock frequency. The approach eliminates the need for a separate RF synthesizer and takes advantage of an existing high-quality (but low frequency) reference source.