1 Introduction

The LMX1204 is a high-frequency clock distribution device that supports up to 12.8 GHz. The device supports four outputs (each with a SYSREF output) and an additional low-frequency output designed for clocking an FPGA. The LMX1204 is designed for distributing a high-frequency clock to multiple RF sampling devices used in phased-array systems. In cases where more outputs are needed, the LMX1204 devices can be cascaded to multiply the number of outputs with negligible impact to clock quality. For the large phased-array systems, maintaining tight timing between the outputs is critical to make sure received signals line up properly.

The LMX1204 Reference Design cascades two layers of the LMX1204 device to distribute a clock to 16 outputs. Figure 1-1 shows a block diagram of the reference design. The cascaded approach is designed for clocking an array of AFE7950 RF sampling transceivers that support a 64T64R array system as depicted in Figure 1-2.

This note outlines measurements on an LMX1204 Reference Design designed to analyze the phase-error response in a typical configuration. This document is not intended to be a full characterization of the LMX1204 device itself as this reference design includes interconnecting traces and a bank of 0.5-m RF cables on the output. Use this application note as a general guideline for typical performance variation in a realistic configuration.