Each DPLL supports Zero Delay Mode (ZDM) to achieve a deterministic phase relationship between the DPLL reference clock and the ZDM feedback output clock at every boot-up or software reset. All output clocks sourced from a ZDM-configured DPLL become phase aligned through the synchronization (SYNC) feature. A zero-phase delay is attainable across all clocks by inserting analog or digital delays available on the LMK5B33216.

Figure 3-7 demonstrates how select outputs, such as OUT0, can internally feed back to any DPLL as a zero-delay output clock. For additional details on ZDM theory, refer to Multi-Clock Synchronization.

Figure 3-7 DPLL ZDM Synchronization Between Reference Input and OUT0