SNAA396A February   2024  – January 2025 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1800G Market Trend
  5. 2LMK5B33216 for 112G and 224G PAM4 SerDes Applications
  6. 3LMK5B33216 Overview
  7. 4LMK5B33216 Performance
    1. 4.1 RMS Jitter
    2. 4.2 BAW Technology
    3. 4.3 Phase Noise Profile
  8. 5LMK5B33216 Features
    1. 5.1 Frequency and Phase Adjustments
    2. 5.2 Input Reference Switching
    3. 5.3 Holdover
    4. 5.4 Zero-Delay Mode
  9. 6Summary
  10. 7References
  11. 8Revision History

4.3 Phase Noise Profile

The output phase noise profile of a network synchronizer like the LMK5B33216 can be broken down into four dominating regions:

  • Below the DPLL LBW
  • Between the DPLL and APLL LBWs
  • Above the APLL LBW
  • Output noise floor

The quality of the DPLL reference and XO, TCXO, and OCXO inputs impact the close-in phase noise of an output clock. The DPLL LBW is a low-pass filter to the DPLL reference clocks. The DPLL reference primarily impacts the output noise profile at carrier offsets less than the DPLL LBW. The DPLL can be configured with a narrower LBW (such as 10Hz) for applications where close-in phase noise matters and noisy references are used as the DPLL inputs. Otherwise, either 10Hz or 100Hz are common settings that can be used since the DPLL reference does not impact the jitter at carrier offsets from 12kHz to 20MHz. Figure 4-5 and Figure 4-5 are examples of phase noise plots with outputs sourced from the VCBO. These plots demonstrate the negligible effect of jitter across 12kHz to 20MHz with different DPLL LBWs.

Above the DPLL LBW, the DPLL reference is attenuated and a combination of the XO/TCXO/OCXO input and the APLL noise dominates up until the APLL LBW. To take advantage of the excellent VCBO performance, the BAW APLL is configured with a narrow LBW, typically 3kHz to 5kHz; as a result, the VCBO dominates the phase noise in the carrier offset range of 8kHz to around 400kHz. Lastly, the noise floor is set by the output buffer, beginning at approximately 1MHz carrier offset.

Thanks to the ultra-low noise VCBO, a low frequency XO (such as 12.8MHz) can be used for the LMK5B33216 without significantly impacting the total RMS jitter, thereby lowering the total design cost.

Figure 4-4 provides a summarized illustration of how each region affects the phase noise of an output clock.

General Phase Noise Plot of a Network Synchronizer Output Clock

A: DPLL loop bandwidth can be set between 1mHz to 4kHz.
B: APLL loop bandwidth for VCBO can be set between 1kHz and 10kHz.
C: APLL loop bandwidth for LC VCO can be set between 100kHz and 1MHz.

Figure 4-4 General Phase Noise Plot of a Network Synchronizer Output Clock
Phase Noise Breakdown of an LMK5B33216 Output Using a 10Hz DPLL LBWFigure 4-5 Phase Noise Breakdown of an LMK5B33216 Output Using a 10Hz DPLL LBW
Phase Noise Breakdown of an LMK5B33216 Output Using a 100Hz DPLL LBWFigure 4-6 Phase Noise Breakdown of an LMK5B33216 Output Using a 100Hz DPLL LBW