SNAA396A February   2024  â€“ January 2025 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1800G Market Trend
  5. 2LMK5B33216 for 112G and 224G PAM4 SerDes Applications
  6. 3LMK5B33216 Overview
  7. 4LMK5B33216 Performance
    1. 4.1 RMS Jitter
    2. 4.2 BAW Technology
    3. 4.3 Phase Noise Profile
  8. 5LMK5B33216 Features
    1. 5.1 Frequency and Phase Adjustments
    2. 5.2 Input Reference Switching
    3. 5.3 Holdover
    4. 5.4 Zero-Delay Mode
  9. 6Summary
  10. 7References
  11. 8Revision History

Holdover

Holdover occurs when the DPLL reference clocks become unavailable, as seen in Figure 5-4. During holdover, the APLL numerator is set by the DPLL tuning word history, which determines the output frequency accuracy upon entry into holdover—any error on entry is considered a short-term holdover error. The tuning word history can be configured as either the accumulated averaged reference phase history, a user-specified value, or the last APLL numerator value.

The quality of the external oscillator (provided to XO input) determines the long-term frequency stability and accuracy of the output frequency. Over time, temperature fluctuations impact the frequency accuracy of the output clocks. Hence, the decision to choose between an XO, TCXO, or OCXO lies primarily on the long-term holdover requirements of the system.

 Holdover FunctionalityFigure 5-4 Holdover Functionality
Reference failure is detected by the device as the DPLL references (INx) are lost.
The DPLL enters holdover and outputs remain phase or frequency locked with a small frequency delta.
The output frequency drifts; the long-term holdover stability is based on the XO/TCXO/OCXO input accuracy.

For applications requiring output frequency correction during long-term holdover, the output frequency can be corrected by making APLL DCO adjustments through software to compensate for temperature variations, as shown in Figure 5-5.

 APLL DCO Operation During HoldoverFigure 5-5 APLL DCO Operation During Holdover