112G PAM-4 SerDes technology is designed to transmit data at 112 gigabits per second (Gbps). 800G switch technology has made significant leaps forward in data networking by leveraging 112G PAM-4 SerDes. For more details on PAM-4 applications, refer to Understanding Clocking Needs for High-Speed 56G PAM-4 Serial Links.

The 800G high-speed switches are engineered to meet increasing data center and telecommunication demands. The 800G switches have a port speed of 800 Gbps that provides bandwidth for rapid data transmission which reduces network congestion for data processing, storage, and distribution. The 800G switches have fast transmission rates, often measured in terabits per second, that handle immense volumes of data generated by virtualization and high-performance computing.

Clocking in high-speed SerDes systems plays an important role in data synchronization and communication reliability. A SerDes has an integrated PLL that clocks out high-speed serial data while maintaining phase-lock to a reference clock. A high-speed SerDes relies on a precise clocking mechanism to maintain proper timing and accurate serialization and deserialization of data. Therefore, providing a low-jitter clock to the integrated SerDes PLL is necessary.

Incorporating a low-jitter clock is achievable by using an external-network synchronizer or jitter cleaner to reduce the noise propagated onto the serial data. A network synchronizer allows the flexibility of switching between various inputs of different frequencies and phase domains without disrupting the SerDes reference.

TI network synchronizers and jitter cleaners with integrated BAW, such as the LMK5B33216, are designed to provide the reference clocks to the SerDes and to support 800G or higher throughputs of data in real-time communication, AI, or IOT applications.

Figure 1-1 demonstrates a simplified block diagram of a 112G and 224G PAM-4 SerDes clock input sourced from the LMK5B33216.