3 LMK5B33216 for Ethernet Applications

The LMK5B33216 is used to jitter-clean SyncE or PHY recovered clocks and provide synchronized, low-jitter, outputs to the ASIC and CPU. For SyncE input clocks, TI recommends setting the DPLL LBW between 1Hz and 3Hz to filter out SyncE transient noise.

Figure 3-1 shows the full system design for a 400G and 800G switch using the LMK5B33216. Pairing the LMK6Cx (TI’s BAW-based LVCMOS oscillator family) with the LMK5B333216 yields a low-cost option for the XO input. Additional clocks can be fanned out to the ASIC through a 4, 8, 12, or 16 output, low additive jitter, and clock buffer from the LMK1Dxxxx family, such as the LMK1D1204.

The LMK3H0102 is a reference-less, BAW-based, clock generator used to clock up to two PCIe Gen 1 to PCIe Gen 6 compliant outputs. Each LMK3H0102 output is capable of generating any frequency between 2.5MHz and 400MHz by dividing down from two fractional output dividers (FODs).

Figure 3-1 Full System Design for 400G and 800G Switch Applications