SNAA396A February 2024 – January 2025 LMK5B33216 , LMK5B33414
Designed for 800G switch applications, the LMK5B33216 is a high-performance network synchronizer that meets the stringent Ethernet-based networking requirements for jitter, rise or fall time, hitless switching, and holdover.
Table 4-1 compares the performance of the LMK5B33216 output clock with the SerDes core reference clock requirements used in 800G switch applications. Figure 4-1 and Figure 4-2 show the LMK5B33216 output phase noise performance meeting the 112G and 224G PAM4 SerDes requirements, respectively. Both output phase noise plots are attained when using a 48MHz TCXO input clock. The LMK5B33216 exceeds the requirements of the 112G and 224G PAM4 SerDes reference clock with the low-noise performance of the Voltage-Controlled BAW Oscillator (VCBO).
Parameter | Example 112G and 224G PAM4 SerDes Core Reference Clock | LMK5B332161 | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||
Frequency | – | 312.5 | – | – | 312.5 | – | MHz |
RMS jitter (12kHz to 20MHz) | – | – | 100 | – | 422 | 602 | fs |
RMS jitter (12kHz to 20MHz) with 4MHz HPF | – | – | 112G PAM4: 90 224G PAM4: 35 | – | 24 | – | fs |
Reference clock phase noise at 100kHz | – | – | -137 | – | -146 | – | dBc/Hz |
Reference clock phase noise at 1MHz | – | – | -143 | – | -159 | – | dBc/Hz |
Reference clock phase noise at 10MHz | – | – | -158 | – | -160 | — | dBc/Hz |
Differential peak-to-peak voltage swing | 800 | – | 1400 | 670 | – | 2300 | mVpp |
Rise or fall time (20% to 80%) | – | 300 | 400 | 175 | 230 | 300 | ps |
Operating ambient temperature | – | – | – | -40 | – | 85 | °C |