SNAA396 February   2024 LMK5B33216 , LMK5B33216 , LMK5B33414 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 800G Market Trend
  5. 2LMK5B33216 for SerDes Applications
    1. 2.1 BAW Technology in LMK5B33216
  6. 3LMK5B33216 for Ethernet Applications
    1. 3.1 Frequency and Phase Adjustments
    2. 3.2 Input Reference Switching
    3. 3.3 Holdover
    4. 3.4 Zero-Delay Mode
  7. 4LMK5B33216 Performance
    1. 4.1 Phase Noise Profile
    2. 4.2 RMS Jitter
  8. 5Summary
  9. 6References

4 LMK5B33216 Performance

The LMK5B33216 meets the challenging requirements of advanced high-speed communication networks such as 800 Gbps systems.

Output clocks generated from the BAW APLL achieve excellent output RMS jitter and phase noise performance for these industries. The VCBO of the BAW APLL operates at 2500MHz (± 100ppm) and can be divided down to output 312.5MHz clocks with 42fs typical and 60fs maximum RMS jitter (12kHz to 20MHz) regardless of the DPLL reference clock frequency and jitter characteristics. The remaining APLLs are LC-VCOs and can be used for additional frequency domains if other phase domains are required outside the Ethernet domain, for example, when the frequency cannot be sourced from the BAW APLL.