SNAA396A February   2024  – January 2025 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1800G Market Trend
  5. 2LMK5B33216 for 112G and 224G PAM4 SerDes Applications
  6. 3LMK5B33216 Overview
  7. 4LMK5B33216 Performance
    1. 4.1 RMS Jitter
    2. 4.2 BAW Technology
    3. 4.3 Phase Noise Profile
  8. 5LMK5B33216 Features
    1. 5.1 Frequency and Phase Adjustments
    2. 5.2 Input Reference Switching
    3. 5.3 Holdover
    4. 5.4 Zero-Delay Mode
  9. 6Summary
  10. 7References
  11. 8Revision History

4 LMK5B33216 Performance

Designed for 800G switch applications, the LMK5B33216 is a high-performance network synchronizer that meets the stringent Ethernet-based networking requirements for jitter, rise or fall time, hitless switching, and holdover.

Table 4-1 compares the performance of the LMK5B33216 output clock with the SerDes core reference clock requirements used in 800G switch applications. Figure 4-1 and Figure 4-2 show the LMK5B33216 output phase noise performance meeting the 112G and 224G PAM4 SerDes requirements, respectively. Both output phase noise plots are attained when using a 48MHz TCXO input clock. The LMK5B33216 exceeds the requirements of the 112G and 224G PAM4 SerDes reference clock with the low-noise performance of the Voltage-Controlled BAW Oscillator (VCBO).

Table 4-1 Comparison Between an Example SerDes Core Reference Clock and LMK5B33216 Output
ParameterExample 112G and 224G PAM4 SerDes Core Reference Clock LMK5B332161UNIT
MINTYPMAXMINTYPMAX
Frequency–312.5––312.5–MHz
RMS jitter (12kHz to 20MHz)––100–422602fs
RMS jitter (12kHz to 20MHz) with 4MHz HPF––112G PAM4: 90
224G PAM4: 35		–24–fs
Reference clock phase noise at 100kHz––-137–-146–dBc/Hz
Reference clock phase noise at 1MHz––-143–-159–dBc/Hz
Reference clock phase noise at 10MHz––-158–-160—dBc/Hz
Differential peak-to-peak voltage swing800–1400670–2300mVpp
Rise or fall time (20% to 80%)–300400175230300ps
Operating ambient temperature–––-40–85°C
(1) The measurements are taken using a 48MHz TCXO as the XO input. All LMK5B33216 outputs are set to the same frequency and sourced from the BAW APLL (APLL3).
(2) The BAW APLL post divider is 8 and the output swing (VOD) is ≥ 800mV.
LMK5B33216 Output Phase Noise Plot with 112G PAM4 SerDes Mask OverlayedFigure 4-1 LMK5B33216 Output Phase Noise Plot with 112G PAM4 SerDes Mask Overlayed
LMK5B33216 Output Phase Noise with 4MHz HPFFigure 4-2 LMK5B33216 Output Phase Noise with 4MHz HPF