Each DPLL supports hitless reference switching with a minimal phase hit through a phase cancellation scheme (also known as phase buildout) and offers an optional phase slew control feature.

The outputs maintain the same phase with hitless switching, with only minor disturbance from before the reference switch, to after the reference switch, as illustrated in Figure 3-3. Without hitless switching, there is a risk of the outputs getting phase hits, which can propagate to the downstream clocks and cause misalignment across data packets. The phase hit is equal to the phase offset between the two reference clocks.

A: OUTx is locked to IN0 with the same phase.

B: IN0 is lost and the DPLL switches reference from IN0 to IN1 without affecting the phase on OUTx.

C: OUTx is locked to IN1 without changing the phase.

Figure 3-3 Phase Cancellation Enabled for Switching Reference With Minor Phase Hits

The outputs gradually adjust phase after a hitless switch when using the phase slew control feature. The phase transitions from the original to the new reference at a rate defined by the programmed phase slew rate. This feature is demonstrated in Figure 3-4.

A. OUTx is locked to IN0 with the same phase.

B. IN0 is lost and the DPLL switches reference from IN0 to IN1.

C. The phase of OUTx gradually changes at a rate defined by the programmed phase slew rate.

D. OUTx is locked to IN1 with the same phase.

Figure 3-4 Phase Slew Control Enabled to Provide a Steady Output Phase Change When Switching Inputs.