SNAA396 February   2024 LMK5B33216 , LMK5B33216 , LMK5B33414 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 800G Market Trend
  5. 2LMK5B33216 for SerDes Applications
    1. 2.1 BAW Technology in LMK5B33216
  6. 3LMK5B33216 for Ethernet Applications
    1. 3.1 Frequency and Phase Adjustments
    2. 3.2 Input Reference Switching
    3. 3.3 Holdover
    4. 3.4 Zero-Delay Mode
  7. 4LMK5B33216 Performance
    1. 4.1 Phase Noise Profile
    2. 4.2 RMS Jitter
  8. 5Summary
  9. 6References

Abstract

Hyper-scale data centers and telecommunication market sectors are currently driving the need for high speed serial links using 112G and 224G Pulse Amplitude Modulation with 4-Levels Serializer and Deserializer (PAM-4 SerDes). The higher data speeds lower the jitter budget for the reference clock to less than 100 fs RMS. TI offers a complete clocking design for high-speed serial links using 112G and future 224G PAM-4 SerDes. The design includes the LMK5B33216 and LMK5B33414 network synchronizers, single-ended and differential buffers, BAW-based oscillators and reference-less clock generators.

TI's Bulk Acoustic Wave (BAW) technology offers industry-leading, ultra-low jitter clocks critical for 112G and 224G PAM-4 SerDes. The LMK5B33216 achieves 42fs RMS typical for 312.5MHz (12kHz to 20MHz) thanks to the low-noise performance of the Voltage-Controlled BAW Oscillator (VCBO). In addition, the LMK5B33216 meets the jitter, rise or fall time, hitless switching, and holdover requirements of 800G reference clocks.