Abstract

Hyperscale data centers and telecommunication market sectors are currently driving the need for high speed serial links using 112G and 224G Pulse Amplitude Modulation with 4-Levels Serializer and Deserializer (PAM4 SerDes). The higher data speeds lower the jitter budget for the 312.5MHz reference clock to less than 100fs RMS for 112G and 35fs RMS with 4MHz high pass filter (HPF) for 224G PAM4 SerDes.

TI's Bulk Acoustic Wave (BAW) technology offers industry-leading, ultra-low jitter clocks critical for the 112G and 224G PAM4 SerDes. The LMK5B33216 achieves 42fs RMS typical and 24fs RMS typical with 4MHz HPF filter for 312.5MHz outputs, meeting the 112G and 224G PAM4 SerDes requirements with a greater margin. In addition, the LMK5B33216 meets the jitter, rise or fall time, hit less switching, and holdover requirements of the 112G and 224G PAM4 SerDes reference clocks.

TI offers a complete clocking design for data center applications as shown in Figure 1-1. This application note examines the clocking design specifically for 800G switches (ToR, leaf, spine, fabric, edge, or aggregation). The switch clocking design includes the LMK5B33216 or LMK5B33414 network synchronizer, single-ended and differential buffers, BAW-based oscillators and reference-less clock generators.

Figure 1-1 Data Center Clocking Design