In an effort to reduce cost and simplify BOM, designers of some systems want to drive multiple loads with a single clock source in applications where the signal integrity of the clock is not critical. Low frequency, single-ended LVCMOS clock signals can be a good target for this type of cost reduction since jitter requirements are usually relaxed and the cost of an oscillator can be relatively high relative to the receiver that this is clocking. However, this technique can raise a number of questions about the specific routing implementation and the affect on signal integrity. How does co-location of loads affect signal integrity? What is the longest acceptable trace length between multiple loads? How many receivers can a single clock source drive while maintaining acceptable rise or fall times, and how does this affect ringing and signal reflections? This application note discusses the transmission line effects of splitting a trace into multiple loads, and provides some recommended topologies based on IBIS simulation results using the LMK6C and CDC6C low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVCMOS oscillators.