SNAA410 July 2024 CDCDB2000 , LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204
To summarize:
BYTE | BITS | TI NAME | RENESAS NAME | Register Differences between 9XQL2001B and LMKDB1120 that Affect Drop-In Replacements | Design Requirements when Replacing the 9QXL2001B with the LMKDB1120 |
---|---|---|---|---|---|
R0 | 7:0 | Output Enable Controls | Output Enable | No difference | N/A. |
R1 | 7:0 | ||||
R2 | 7:0 | ||||
R3 | 7:0 | OE Pin Readback | OE# Pin Readback | ||
R4 | 7:5 | Reserved | Reserved | No difference | |
4 | AOD Enable Control | Reserved | Completing a drop-in replacement does not require any software changes on this bit. The 9QXL2001B's R4[4] is reserved while the LMKDB1120's R4[4] offers an additional automatic output disable function. The LMKDB1120's default value at POR matches the 9QXL2001B's default. | ||
3:1 | Reserved | Reserved | No difference | ||
0 | SBI_EN Readback | SBEN Readback | |||
R5 | 7:0 | Device Info | Vendor & Revision ID | No difference | |
R6 | 7:0 | Device Info (cont.) | Device ID | ||
R7 | 7:0 | SMBus Byte Counter | Byte Count | ||
R8 | 7:0 | SBI Mask | Side Bank Mask | ||
R9 | 7:0 | ||||
R10 | 7:0 | ||||
R20 |
7 |
AMP_1 |
AMP[2] |
The 9QXL2001B global differential output control register (20[7:5]) spreads across 3 bits to represent global output amplitudes from 0.3V through 1V in 100mV step. The LMKDB1120 global differential output control register (R20[7:4]) spreads across 4 bits to represent global output amplitudes from 0.6V through 1V in 25mV steps. Both of these parts have the same default global output amplitude at POR of 0.75V. | If not using the default global output
amplitude of the 9QXL2001B, program bits R20[7:4] of the LMKDB1120
as follows: 0h = 600mV 1h = 625mV 2h = 650mV 3h = 675mV 4h = 700mV 5h = 725mV 6h = 750mV 7h = 775mV 8h = 800mV 9h = 825mV Ah = 850mV Bh = 875mV Ch = 900mV Dh = 925mV Eh = 950mV Fh = 975mV |
6 | AMP[1] | ||||
5 | AMP[0] | ||||
4 | Reserved | ||||
3:2 | Reserved | Reserved | No difference | N/A. | |
1 | STOPST[1] | The LMKDB1120 does not have differential stop mode state control like the 9QXL2001B. The default of both parts is the same (set to 0x0 = Low/Low). TI followed DB200QL's definition differential stop mode default which does not require modifications. | Do not program these registers on the LMKDB1120. Leave the POR value of 0x0 unchanged. | ||
0 | STOPTS[0] | ||||
R21 | 7 | RX1_EN_AC_INPUT | Reserved | Completing a drop-in replacement does not require any software changes on these bits. The 9QXL2001B 21[7:6] are reserved and have the same default POR values as the LMKDB1120. The LMKDB1120 R21[7:6] offer additional input functions: enabling a receiver bias when CLKIN1 is AC coupled and enabling an internal 50Ω input termination on CLKIN1. | N/A. |
6 | RX1_EN_RTERM_LSB | ||||
5:4 | Reserved | Reserved | No difference | ||
3 | PD_RESTORB | PD_RESTORE# | |||
2 | SDATA_TIMEOUT_EN | Reserved | Completing a drop-in replacement does not require any software changes on this bit. The 9QXL2001B 21[2] is reserved while the LMKDB1120 R21[2] offers an additional SMBus SDATA time out monitoring function. The LMKDB1120's default value at POR matches the 9QXL2001B's default. | ||
1 | Reserved | Reserved | No difference | ||
0 | LOSb_RB | Reserved | Completing a drop-in replacement does not require any software changes on this bit. The 9QXL2001B's 21[0] is reserved while the LMKDB1120's R21[0] offers an additional readback of LOS detect clock output function. The LMKDB1120's default value at POR matches the 9QXL2001B's default. |