8.3.1 DAC Section

The DAC121C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer.

For simplicity, a single resistor string is shown in Figure 20. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of:

D can take on any integer value from 0 to 4095. This configuration ensures that the DAC is monotonic.

Figure 20. DAC Resistor String

8.3.2 Output Amplifier

The output amplifier is rail-to-rail, providing an output voltage range of 0 V to V_A when the reference is V_A. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and V_A, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than V_A, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in the Electrical Characteristics.

The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to V_A. The zero-code and full-scale outputs for given load currents are available in the Electrical Characteristics.

8.3.3 Reference Voltage

The DAC121C081 uses the supply (V_A) as the reference. With that said, V_A must be treated as a reference. The analog output is only as clean as the reference (V_A). TI recommends driving the reference with a voltage source with low-output impedance.

The DAC121C085 comes with an external reference supply pin (V_REF). For the DAC121C085, it is important that V_REF be kept as clean as possible.

Applications Information describes a handful of ways to drive the reference appropriately. See Using References as Power Supplies for details.

8.3.4 Serial Interface

The I²C-compatible interface operates in all three speed modes. Standard mode (100 kHz) and Fast mode (400 kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document. The following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistor values depends on the total bus capacitance and operating speed.

8.3.4.1 Basic I²C Protocol

The I²C interface is bi-directional and allows multiple devices to operate on the same bus. To facilitate this bus configuration, each device has a unique hardware address which is referred to as the slave address. To communicate with a particular device on the bus, the controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a Stop condition on the bus.

All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is more complicated. See High-Speed (Hs) Mode for the full details of a Hs-mode Start condition. A Repeated Start is generated to either address a different device, or switch between read and write modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 21. The bus continues to operate in the same speed mode as before the Repeated Start condition.

All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop condition occurs when SDA is pulled from low to high while SCL is high. After a Stop condition, the bus remains idle until a master generates a Start condition.

See the Phillips I2C® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial interface.

Figure 21. Basic Operation

8.3.4.3 High-Speed (Hs) Mode

For Hs-mode, the sequence of events to begin communication differ slightly from Standard-Fast mode. Figure 22 describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master generates a Start condition and sends the 8-bit Hs master code (00001XXX) to the DAC121C081. Next, the DAC121C081 responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to Hs-mode by increasing the bus speed and generating a Repeated Start condition (driving SDA low while SCL is pulled high). At this point, the master sends the slave address to the DAC121C081, and communication continues as shown in Figure 21.

When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode again before increasing the bus speed and switching to Hs-mode. ns16705

Figure 22. Beginning Hs-Mode Communication

8.3.5 Power-On Reset

The power-on reset circuit controls the output voltage of the DAC during power up. Upon application of power, the DAC register is filled with zeros and the output voltage is 0 V. The output remains at 0 V until a valid write sequence is made to the DAC.

When resetting the device, it is crutial that the V_A supply be lowered to a maximum of 200 mV before the supply is raised again to power up the device. Dropping the supply to within 200 mV of GND during a reset will ensure the ADC performs as specified.

8.3.6 Simultaneous Reset

The broadcast address allows the I²C master to write a single word to multiple DACs simultaneously. Provided that all of the DACs exist on a single I²C bus, every DAC updates when the broadcast address is used to address the bus. This feature allows the master to reset all of the DACs on a shared I²C bus to a specific digital code. For instance, if the master writes a power-down code to the bus with the broadcast address, all of the DACs powers down simultaneously.

8.3.7 Additional Timing Information: t_outz

The t_outz specification is provided to aid the design of the I²C bus. After the SCL bus is driven low by the I²C master, the SDA bus will be held for a short time by the DAC121C081. This time is referred to as t_outz. The following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the DAC begins to transition the SDA bus. The t_outz specification only applies when the DAC is in control of the SDA bus. The DAC is only in control of the bus during an ACK by the DAC121C081 or a data byte read from the DAC (see Figure 25).

Figure 23. Data Output Timing

The t_outz specification is typically 87 ns in Standard-Fast Mode and 38 ns in Hs-Mode.

8.4.1 Power-Down Modes

The DAC121C081 has three power-down modes. In power-down mode, the supply current drops to 0.13 µA at 3 V and 0.15 µA at 5 V (typical). The DAC121C081 is put into power-down mode by writing a one to PD1 and/or PD0. The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND (see Figure 26).

The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the power-down modes. When the DAC121C081 is powered down, the value written to the DAC register, including the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and V_OUT will be updated with the new 12-bit data value.

The time to exit power-down (Wake-Up Time) is typically 0.8 µs at 3 V and 0.5 µs at 5 V.

8.5.1 Writing to the DAC Register

To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a zero to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or generates a Repeated Start condition to begin communication with another device on the bus. Until generating a Stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.

Figure 24. Typical Write to the DAC Register

8.5.2 Reading from the DAC Register

To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes a one to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a Stop condition to end communication, or a Repeated Start condition to begin communication with another device on the bus.

Figure 25. Typical Read from the DAC Register

8.6.1 DAC Register

The DAC register, Figure 26, has sixteen bits. The first two bits are always zero. The next two bits determine the mode of operation (normal mode or one of three power-down modes). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with twelve 0s corresponding to an output of 0 V and twelve 1s corresponding to a full-scale output of V_A – 1 LSB. When writing to the DAC Register, V_OUT will update on the rising edge of the ACK following the lower data byte.

Figure 26. DAC Register Contents