SNAS663B March   2017  – July 2019 LMK04616

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Simplified Schematic
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Device Support
      1. 5.1.1 Development Support
        1. 5.1.1.1 Clock Design Tool
        2. 5.1.1.2 Clock Architect
        3. 5.1.1.3 TICS Pro
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Community Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  6. 6Mechanical, Packaging, and Orderable Information

3 Description

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO.

Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use.

Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems.

Device Information(1)

PART NUMBER VCO FREQUENCY
LMK04616 5870 MHz to 6175 MHz
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

LMK04616 g_frontpage_461x_v2.gif