SNAS668E August 2015 – September 2024 LMK03328
PRODUCTION DATA
IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a reference clock that is within ±100 ppm of the nominal frequency. In the worst case, an RX node with the local reference clock at –100 ppm from the nominal frequency must be able to work seamlessly with a TX node that has a dedicated local reference clock at +100 ppm from the nominal frequency. Without any clock compensation on the RX node, the read pointer severely lags behind the write pointer and causes FIFO overflow errors. On the contrary, when the local clock of the RX node operates at +100 ppm from the nominal frequency and the local clock of the TX node operates at –100 ppm from the nominal frequency, FIFO underflow errors occur without any clock compensation.
To prevent such overflow and underflow errors from occurring, modern ASICs and FGPAs include a clock compensation scheme that introduces elastic buffers. Such a system, shown in Figure 10-1, is validated thoroughly during the validation phase by interfacing slower nodes with faster ones and reinforce compliance to IEEE802.3. The LMK03328 provides the ability to fine tune the frequency of the outputs based on changing the on-chip load capacitance when operated with a crystal input. This fine tuning can be performed through I2C or through the GPIO5 pin as described in Crystal Input Interface (SEC_REF). A total of ±50-ppm frequency tuning is achievable when using pullable crystals whose C0/C1 ratio is less than 250. The change in load capacitance is implemented in a manner such that the outputs of the LMK03328 undergo a smooth monotic change in frequency.