SNAS668E August   2015  – September 2024 LMK03328

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics - Power Supply
    7. 6.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 6.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 6.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 6.10 VCO Characteristics
    11. 6.11 PLL Characteristics
    12. 6.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 6.13 LVCMOS Output Characteristics (STATUS[1:0]
    14. 6.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 6.15 AC-LVPECL Output Characteristics
    16. 6.16 AC-LVDS Output Characteristics
    17. 6.17 AC-CML Output Characteristics
    18. 6.18 HCSL Output Characteristics
    19. 6.19 Power-On/Reset Characteristics
    20. 6.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 6.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 6.22 Analog Input Characteristics (GPIO[5])
    23. 6.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 6.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics
    25. 6.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics
    26. 6.26 Closed-Loop Output Jitter Characteristics
    27. 6.27 PCIe Clock Output Jitter
    28. 6.28 Typical Power Supply Noise Rejection Characteristics
    29. 6.29 Typical Power Supply Noise Rejection Characteristics
    30. 6.30 Typical Closed-Loop Output Spur Characteristics
    31. 6.31 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Block-Level Description
      2. 8.3.2 Device Configuration Control
        1. 8.3.2.1 Hard Pin Mode (HW_SW_CTRL = 1)
          1. 8.3.2.1.1 PLL Blocks
          2. 8.3.2.1.2 Output Buffer Auto Mute
          3. 8.3.2.1.3 Input Block
          4. 8.3.2.1.4 Channel Mux
          5. 8.3.2.1.5 Output Divider
          6. 8.3.2.1.6 Output Driver Format
          7. 8.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 8.3.2.2 Soft Pin Programming Mode (HW_SW_CTRL = 0)
          1. 8.3.2.2.1 Device Config Space
          2. 8.3.2.2.2 PLL Blocks
          3. 8.3.2.2.3 Output Buffer Auto Mute
          4. 8.3.2.2.4 Input Block
          5. 8.3.2.2.5 Channel Mux
          6. 8.3.2.2.6 Output Divider
          7. 8.3.2.2.7 Output Driver Format
          8. 8.3.2.2.8 Status MUX, Divider, and Slew Rate
        3. 8.3.2.3 Register File Reference Convention
    4. 8.4 Device Functional Modes
      1. 8.4.1  Smart Input MUX
      2. 8.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 8.4.3  Crystal Input Interface (SEC_REF)
      4. 8.4.4  Reference Doubler
      5. 8.4.5  Reference (R) Divider
      6. 8.4.6  Input (M) Divider
      7. 8.4.7  Feedback (N) Divider
      8. 8.4.8  Phase Frequency Detector (PFD)
      9. 8.4.9  Charge Pump
      10. 8.4.10 Loop Filter
      11. 8.4.11 VCO Calibration
      12. 8.4.12 Fractional Circuitry
        1. 8.4.12.1 Programmable Dithering Levels
        2. 8.4.12.2 Programmable Delta Sigma Modulator Order
      13. 8.4.13 Post Divider
      14. 8.4.14 High-Speed Output MUX
      15. 8.4.15 High-Speed Output Divider
      16. 8.4.16 High-Speed Clock Outputs
      17. 8.4.17 Output Synchronization
      18. 8.4.18 Status Outputs
        1. 8.4.18.1 Loss of Reference
        2. 8.4.18.2 Loss of Lock (LOL)
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
      8. 8.5.8 Read ROM
      9. 8.5.9 Default Device Configurations in EEPROM and ROM
  10. 9 Register Maps
    1. 9.1 LMK03328 Registers
      1. 9.1.1   VNDRID_BY1 Register; R0
      2. 9.1.2   VNDRID_BY0 Register; R1
      3. 9.1.3   PRODID Register; R2
      4. 9.1.4   REVID Register; R3
      5. 9.1.5   PARTID Register; R4
      6. 9.1.6   PINMODE_SW Register; R8
      7. 9.1.7   PINMODE_HW Register; R9
      8. 9.1.8   TARGETADR Register; R10
      9. 9.1.9   EEREV Register; R11
      10. 9.1.10  DEV_CTL Register; R12
      11. 9.1.11  INT_LIVE Register; R13
      12. 9.1.12  INT_MASK Register; R14
      13. 9.1.13  INT_FLAG_POL Register; R15
      14. 9.1.14  INT_FLAG Register; R16
      15. 9.1.15  INTCTL Register; R17
      16. 9.1.16  OSCCTL2 Register; R18
      17. 9.1.17  STATCTL Register; R19
      18. 9.1.18  MUTELVL1 Register; R20
      19. 9.1.19  MUTELVL2 Register; R21
      20. 9.1.20  OUT_MUTE Register; R22
      21. 9.1.21  STATUS_MUTE Register; R23
      22. 9.1.22  DYN_DLY Register; R24
      23. 9.1.23  REFDETCTL Register; R25
      24. 9.1.24  STAT0_INT Register; R27
      25. 9.1.25  STAT1 Register; R28
      26. 9.1.26  OSCCTL1 Register; R29
      27. 9.1.27  PWDN Register; R30
      28. 9.1.28  OUTCTL_0 Register; R31
      29. 9.1.29  OUTCTL_1 Register; R32
      30. 9.1.30  OUTDIV_0_1 Register; R33
      31. 9.1.31  OUTCTL_2 Register; R34
      32. 9.1.32  OUTCTL_3 Register; R35
      33. 9.1.33  OUTDIV_2_3 Register; R36
      34. 9.1.34  OUTCTL_4 Register; R37
      35. 9.1.35  OUTDIV_4 Register; R38
      36. 9.1.36  OUTCTL_5 Register; R39
      37. 9.1.37  OUTDIV_5 Register; R40
      38. 9.1.38  OUTCTL_6 Register; R41
      39. 9.1.39  OUTDIV_6 Register; R42
      40. 9.1.40  OUTCTL_7 Register; R43
      41. 9.1.41  OUTDIV_7 Register; R44
      42. 9.1.42  CMOSDIVCTRL Register; R45
      43. 9.1.43  CMOSDIV0 Register; R46
      44. 9.1.44  CMOSDIV1 Register; R47
      45. 9.1.45  STATUS_SLEW Register; R49
      46. 9.1.46  IPCLKSEL Register; R50
      47. 9.1.47  IPCLKCTL Register; R51
      48. 9.1.48  PLL1_RDIV Register; R52
      49. 9.1.49  PLL1_MDIV Register; R53
      50. 9.1.50  PLL2_RDIV Register; R54
      51. 9.1.51  PLL2_MDIV Register; R55
      52. 9.1.52  PLL1_CTRL0 Register; R56
      53. 9.1.53  PLL1_CTRL1 Register; R57
      54. 9.1.54  PLL1_NDIV_BY1 Register; R58
      55. 9.1.55  PLL1_NDIV_BY0 Register; R59
      56. 9.1.56  PLL1_FRACNUM_BY2 Register; R60
      57. 9.1.57  PLL1_FRACNUM_BY1 Register; R61
      58. 9.1.58  PLL1_FRACNUM_BY0 Register; R62
      59. 9.1.59  PLL_FRACDEN_BY2 Register; R63
      60. 9.1.60  PLL1_FRACDEN_BY1 Register; R64
      61. 9.1.61  PLL1_FRACDEN_BY0 Register; R65
      62. 9.1.62  PLL1_MASHCTRL Register; R66
      63. 9.1.63  PLL1_LF_R2 Register; R67
      64. 9.1.64  PLL1_LF_C1 Register; R68
      65. 9.1.65  PLL1_LF_R3 Register; R69
      66. 9.1.66  PLL1_LF_C3 Register; R70
      67. 9.1.67  PLL2_CTRL0 Register; R71
      68. 9.1.68  PLL2_CTRL1 Register; R72
      69. 9.1.69  PLL2_NDIV_BY1 Register; R73
      70. 9.1.70  PLL2_NDIV_BY0 Register; R74
      71. 9.1.71  PLL2_FRACNUM_BY2 Register; R75
      72. 9.1.72  PLL2_FRACNUM_BY1 Register; R76
      73. 9.1.73  PLL2_FRACNUM_BY0 Register; R77
      74. 9.1.74  PLL2_FRACDEN_BY2 Register; R78
      75. 9.1.75  PLL2_FRACDEN_BY1 Register; R79
      76. 9.1.76  PLL2_FRACDEN_BY0 Register; R80
      77. 9.1.77  PLL2_MASHCTRL Register; R81
      78. 9.1.78  PLL2_LF_R2 Register; R82
      79. 9.1.79  PLL2_LF_C1 Register; R83
      80. 9.1.80  PLL2_LF_R3 Register; R84
      81. 9.1.81  PLL2_LF_C3 Register; R85
      82. 9.1.82  XO_MARGINING Register; R86
      83. 9.1.83  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      84. 9.1.84  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      85. 9.1.85  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      86. 9.1.86  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      87. 9.1.87  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      88. 9.1.88  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      89. 9.1.89  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      90. 9.1.90  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      91. 9.1.91  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      92. 9.1.92  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      93. 9.1.93  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      94. 9.1.94  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      95. 9.1.95  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      96. 9.1.96  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      97. 9.1.97  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      98. 9.1.98  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      99. 9.1.99  XO_OFFSET_SW_BY1 Register; R104
      100. 9.1.100 XO_OFFSET_SW_BY0 Register; R105
      101. 9.1.101 PLL1_CTRL2 Register; R117
      102. 9.1.102 PLL1_CTRL3 Register; R118
      103. 9.1.103 PLL1_CALCTRL0 Register; R119
      104. 9.1.104 PLL1_CALCTRL1 Register; R120
      105. 9.1.105 PLL2_CTRL2 Register; R131
      106. 9.1.106 PLL2_CTRL3 Register; R132
      107. 9.1.107 PLL2_CALCTRL0 Register; R133
      108. 9.1.108 PLL2_CALCTRL1 Register; R134
      109. 9.1.109 NVMSCRC Register; R135
      110. 9.1.110 NVMCNT Register; R136
      111. 9.1.111 NVMCTL Register; R137
      112. 9.1.112 NVMLCRC Register; R138
      113. 9.1.113 MEMADR_BY1 Register; R139
      114. 9.1.114 MEMADR_BY0 Register; R140
      115. 9.1.115 NVMDAT Register; R141
      116. 9.1.116 RAMDAT Register; R142
      117. 9.1.117 ROMDAT Register; R143
      118. 9.1.118 NVMUNLK Register; R144
      119. 9.1.119 REGCOMMIT_PAGE Register; R145
      120. 9.1.120 POR_CTRL Register; R173
      121. 9.1.121 XOCAPCTRL_BY1 Register; R199
      122. 9.1.122 XOCAPCTRL_BY0 Register; R200
    2. 9.2 EEPROM Map
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Jitter Considerations in SERDES Systems
      2. 10.1.2 Frequency Margining
        1. 10.1.2.1 Fine Frequency Margining
        2. 10.1.2.2 Coarse Frequency Margining
    2. 10.2 Typical Applications
      1. 10.2.1 Application Block Diagram Examples
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Device Selection
            1. 10.2.1.2.1.1 Calculation Using LCM
          2. 10.2.1.2.2 Device Configuration
          3. 10.2.1.2.3 PLL Loop Filter Design
            1. 10.2.1.2.3.1 PLL Loop Filter Design
          4. 10.2.1.2.4 PLL and Clock Output Assignment
          5. 10.2.1.2.5 Spur Mitigation Techniques
            1. 10.2.1.2.5.1 Phase Detector Spurs
            2. 10.2.1.2.5.2 Integer Boundary Fractional Spurs
            3. 10.2.1.2.5.3 Primary Fractional Spurs
            4. 10.2.1.2.5.4 Sub-Fractional Spurs
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Device Power-Up Sequence
      2. 10.3.2 Device Power-Up Timing
      3. 10.3.3 Power Down
      4. 10.3.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.3.4.1 Mixing Supplies
        2. 10.3.4.2 Power-On Reset
        3. 10.3.4.3 Powering Up From Single-Supply Rail
        4. 10.3.4.4 Powering Up From Split-Supply Rails
        5. 10.3.4.5 Slow Power-Up Supply Ramp
        6. 10.3.4.6 Non-Monotonic Power-Up Supply Ramp
        7. 10.3.4.7 Slow Reference Input Clock Start-Up
      5. 10.3.5 Power Supply Bypassing
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Assess Thermal Reliability
        2. 10.4.1.2 Support for PCB Temperature up to 105°C
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.4.17 Output Synchronization

All output dividers and PLL post dividers can be synchronized using the active-low SYNCN signal. This signal can come from the GPIO0 pin (in soft pin mode only) or from R12.6. The most common method to execute the output synchronization is to toggle the GPIO0 pin. When R56.1 and/or R71.1 are set to 1, to enable synchronization of outputs that are derived from PLL1 and/or PLL2, and GPIO0 pin is asserted (VGPIO0 ≤ VIL), the corresponding output driver or drivers are muted and divider is reset.

Note:

Output-to-output skew specification can only be verified when PLL post divider is greater than 2 and after an output synchronization event.

The latency to reset VCO divider is a sum of:

  • 2 to 3 negative edge of output clock cycles of the largest divided value + “x” nano seconds of asynchronous delay + 2 to 3 VCO clock cycle.
  • If SYNCN occur after rising but before negative edge, sync delay is less 3 clock cycle and closer to 2 clock cycle.
  • The latency is deterministic and the variation is no more than 1 VCO clock cycle. An example scenario is shown in Figure 8-22.
Table 8-6 Output Channel Synchronization
GPIO0 / R12.6OUTPUT DIVIDER AND DRIVER STATE
0Output driver or drivers is tri stated and divider is reset
1Normal output driver/divider operation as configured

Minimum SYNCN pulse width = 3 negative clock edge of slowest output clock cycle + “x” nano second of propagation delay + 3 VCO clock cycle. The synchronization feature is particularly helpful in systems with multiple LMK03328 devices. If SYNCN is released simultaneously for all devices, the total remaining output delay variation is ±1 VCO clock cycles for all devices configured to identical output mux settings. Output enable and disable events are synchronous to minimize glitch and runt pulses. In Soft Pin Mode, the SYNCN control can also be used to disable any outputs to prevent output clocks from being distributed to down stream devices, such as DSPs or FPGAs, until devices are configured and ready to accept the incoming clock.

LMK03328 SYNCN to Output Delay VariationFigure 8-29 SYNCN to Output Delay Variation