SNAS668 Data sheet

SNAS668E August 2015 – September 2024 LMK03328

PRODUCTION DATA

6.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V, VDDO_x = 1.8 V, 2.5 V, 3.3 V, T_A = 25°C, Reference Input = 50 MHz, PFD = 100 MHz, Integer-N PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Post Divider = 8, Output Divider = 4, Output Type = AC-LVPECL/AC-LVDS/AC-CML/HCSL/LVCMOS

PARAMETER ⁽¹⁾⁽²⁾		OUTPUT TYPE					UNIT
phn_10k	Phase noise at 10-kHz offset	–143	–142	–142	–141	–139	dBc/Hz
phn_50k	Phase noise at 50-kHz offset	–143.5	–143	–143	–142	–141	dBc/Hz
phn_100k	Phase noise at 100-kHz offset	–144	–144	–144	–144	–143	dBc/Hz
phn_500k	Phase noise at 500-kHz offset	–146	–146	–146	–146	–145	dBc/Hz
phn_1M	Phase noise at 1-MHz offset	–149.5	–149	–149	–149	–149	dBc/Hz
phn_5M	Phase noise at 5-MHz offset	–160.5	–160	–160	–159	–158	dBc/Hz
phn_20M	Phase noise at 20-MHz offset	–164.5	–164	–164	–161	–159	dBc/Hz
RJ	Random Jitter integrated from 10-kHz to 20-MHz offsets	96	99	99	107	119	fs, RMS

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Jitter specifications apply for differential output formats with low-jitter differential input clock or crystal input. Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single-ended converter (balun or buffer).