All design aspects of the LMK03328 are quite involved, and software support is available to assist in part selection, part programming, loop filter design, and phase noise simulation. This design procedure provides a quick outline of the process.

1. Device Selection
   • Device Selection is the first step to calculate the specified VCO frequency given required output frequencies. The device must be able to produce the VCO frequency that can be divided down to the required output frequencies.
   • The Clock Tree Architect from TI aids in the selection of the right device that meets the designer output frequencies and format requirements.
2. Device Configuration
   • There are many device configurations to achieve the desired output frequencies from a device. However there are some optimizations and trade-offs to be considered.
   • The TI PLLatinum Sim attempts to maximize the phase detector frequency, use smallest dividers, and maximizes PLL charge pump current.
   • The software attempts to use fewer frequency domains where each domain corresponds to an individual PLL.
     Note:

     The LMK03328 incorporates two PLLs and can support two frequency domains.

   • These guidelines below can be followed when configuring PLL related dividers or other related registers:
     • For the lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
     • For the lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge pump currents often have similar performance due to diminishing returns.
     • To reduce loop filter component sizes, increase the N value and/or reduce the charge pump current.
     • To minimize cross coupling between the VCOs of each PLL, keeping a large enough frequency separation between the VCOs is best. For most application use cases, there are two or more VCO frequencies that can result in the same output frequencies by changing the output divider, PLL post divider, and PLL N divider.
     • For fractional divider values, keep the denominator at highest value possible to minimize spurs. Using higher order modulators is also best wherever possible for the same reason.
     • As a typical heuristic, keep the phase detector frequency approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth can be unstable and a phase detector frequency > 100 × loop bandwidth can experience increased lock time due to cycle slipping.
3. PLL Loop Filter Design
   • TI recommends using PLLatinum Sim to design the loop filter.
   • Optimal loop filter design and simulation can be achieved when custom reference phase noise profiles are loaded into the software tool.
   • While designing the loop filter, adjusting the charge pump current or N value can help the loop filter component selection. Lower charge pump currents and larger N values result in smaller component values, but can increase impacts of leakage and reduce PLL phase noise performance.
   • A more detailed understanding of loop filter design can be found in PLL Performance, Simulation, and Design (www.ti.com/tool/pll_book) by Dean Banerjee.
4. Clock Output Assignment
   • The design software does not take into account frequency assignment to specific outputs except to verify that the output frequencies can be achieved. Consider the proximity of the clock outputs to each other and other PLL circuitry when choosing the final clock output locations. The following are some guidelines to help achieve optimal performance when assigning outputs to specific clock output pins.
     • Group common frequencies together.
     • PLL charge pump circuitry can cause crosstalk at the charge pump frequency. Place outputs sharing charge pump frequency or lower priority outputs not sensitive to charge pump frequency spurs together.
     • Keep frequency separation between VCOs as high as possible for minimum cross coupling.
     • For minimizing cross coupling between the PLLs, consider routing PLL2 to any of outputs 0, 1, 2, or 3 and routing PLL1 to any of outputs 4, 5, 6, or 7.
     • Clock output MUXes can create a path for noise coupling. Factor in frequencies which can have some bleedthrough from non-selected mux inputs.
     • If possible, use outputs 0, 1, 2, or 3. These outputs do not have MUX in the clock path and have limited opportunity for cross coupled noise.
5. Device Programming
   • The EVM programming software tool CodeLoader can be used to program the device with the desired configuration.