SNAS669E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
CMOS Output Divider Control. The CMOS Clock Outputs provided on STATUS0 and STATUS1 can come from either CMOS Divider0 or CMOS Divider1. Additionally the clock source routed to the CMOS Dividers can come from either the PLL LVCMOS Pre-Divider or the PLL2 LVCMOS Pre-Divider.
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:6] | RSRVD | RW | 0x0 | Y | Reserved. | |
[5:4] | PLLCMOSPREDIV[1:0] | RW | 0x0 | Y | PLL LVCMOS Pre-Divider Selection. The PLLCMOSPREDIV field selects the divider value for the PLL pre-divider that drives the CMOS Dividers. | |
PLLCMOSPREDIV | Divider Value | |||||
0 (0x0) | Disabled | |||||
1 (0x1) | 4 | |||||
2 (0x2) | 5 | |||||
3 (0x3) | Reserved | |||||
[3:2] | STATUS1MUX[1:0] | RW | 0x2 | Y | STATUS1 Mux Selection. The STATUS1MUX field controls the signal source for the STATUS1 Pin as described below. | |
STATUS1MUX | STATUS1 OPERATION | |||||
0 (0x0) | LVCMOS Clock, from STATUS0 Divider | |||||
1 (0x1) | LVCMOS Clock, from STATUS1 Divider | |||||
2 (0x2) | Normal Status Operation | |||||
3 (0x3) | STATUS1 Disabled | |||||
[1:0] | STATUS0MUX[1:0] | RW | 0x2 | Y | STATUS0 Mux Selection. The STATUS0MUX field controls the signal source for the STATUS0 Pin as described below. | |
STATUS0MUX | STATUS0 OPERATION | |||||
0 (0x0) | LVCMOS Clock, from STATUS0 Divider | |||||
1 (0x1) | LVCMOS Clock, from STATUS1 Divider | |||||
2 (0x2) | Normal Status Operation | |||||
3 (0x3) | STATUS0 Disabled |