SNAS680E December 2015 – August 2022 LMX2582
PRODUCTION DATA
To go below the VCO lower bound, the channel divider must be used. The channel divider consists of three programmable dividers controlled by the registers CHDIV_SEG1, CHDIV_SEG2, CHDIV_SEG3. The Multiplexer (programmed with register CHDIV_SEG_SEL) selects which divider is included in the path. The minimum division is 2 while the maximum division is 192. Un-used dividers can be powered down to save current consumption. The entire channel divider can be powered down with register CHDIV_EN = 0 or selectively setting registers CHDIV_SEG1_EN = 0, CHDIV_SEG2_EN = 0 ,CHDIV_SEG3_EN = 0. Unused buffers may also be powered down with registers CHDIV_DISTA_EN and CHDIV_DIST_EN. There are restrictions on the maximum VCO frequency when channel divider is engaged.
OUTPUT FREQUENCY (MHz) | CHDIV SEGMENT | TOTAL DIVISION | VCO FREQUENCY (MHz) | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | SEG1 | SEG2 | SEG3 | MIN | MAX | |
1775 | 3550 | 2 | 1 | 1 | 2 | 3550 | 7100 |
1184 | 2200 | 3 | 1 | 1 | 3 | 3552 | 6600 |
888 | 1184 | 2 | 2 | 1 | 4 | 3552 | 4736 |
592 | 888 | 3 | 2 | 1 | 6 | 3552 | 5328 |
444 | 592 | 2 | 4 | 1 | 8 | 3552 | 4736 |
296 | 444 | 2 | 6 | 1 | 12 | 3552 | 5328 |
222 | 296 | 2 | 8 | 1 | 16 | 3552 | 4736 |
148 | 222 | 3 | 8 | 1 | 24 | 3552 | 5328 |
111 | 148 | 2 | 8 | 2 | 32 | 3552 | 4736 |
99 | 111 | 3 | 6 | 2 | 36 | 3564 | 3996 |
74 | 99 | 3 | 8 | 2 | 48 | 3552 | 4752 |
56 | 74 | 2 | 8 | 4 | 64 | 3584 | 4736 |
37 | 56 | 2 | 8 | 6 | 96 | 3552 | 5376 |
28 | 37 | 2 | 8 | 8 | 128 | 3584 | 4736 |
20 | 28 | 3 | 8 | 8 | 192 | 3840 | 5376 |