The input signal path contains the components between the input (OSCin) buffer and the phase detector. The best PLL noise floor is achieved with a 200-MHz input signal for the highest dual-phase detector frequency. To address a wide range of applications, the input signal path contains the below components for flexible configuration before the phase detector. Each component can be bypassed. See Table 7-1 for usage boundaries if engaging a component.

• OSCin doubler: This is low noise frequency doubler which can be used to multiply input frequencies by two. The doubler uses both the rising and falling edge of the input signal so the input signal must have 50% duty cycle if enabling the doubler. The best PLL noise floor is achieved with 200-MHz PFD, thus the doubler is useful if, for example, a very low-noise, 100-MHz input signal is available instead.
• Pre-R divider: This is a frequency divider capable of very high frequency inputs. Use this to divide any input frequency up to 1400-MHz, and then the post-R divider if lower frequencies are needed.
• Multiplier: This is a programmable, low noise multiplier. In combination with the Pre-R and Post-R dividers, the multiplier offers the flexibility to set a PFD away from frequencies that may create critical integer boundary spurs with the VCO and output frequencies. See the Section 8 section for an example. The user should not use the doubler while using the low noise programmable multiplier.
• Post-R divider: Use this divider to divide down to frequencies below 5 MHz in extended PFD mode.