SNAS680E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

7.6.1.1 Register Descriptions

Table 7-5 R0 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:14R/WProgram to Register Map default values
13LD_ENR/W1Lock detect enable
1: enable
0: disable
12:9R/WProgram to Register Map default values
8:7FCAL_HPFD_ADJR/W0Used for when PFD freq is high
3: PFD > 200 MHz
2: PFD > 150 MHz
1: PFD > 100 MHz
0: not used
6:5FCAL_LPFD_ADJR/W0Used for when PFD freq is low
3: PFD < 2.5 MHz
2: 2.5 MHz ≤ PFD < 5 MHz
1: 5 MHz ≤ PFD < 10 MHz
0: PFD ≥ 10 MHz
4ACAL_ENR/W1Enable amplitude calibration
1: enable (calibration algorithm will set VCO amplitude. For manual mode set register VCO_IDAC_OVR=1, and then set the VCO amplitude by register VCO_IDAC)
0: disable
3FCAL_ENR/W1Enable frequency calibration
1: enable (writing 1 to this register triggers the calibration sequence)
0: disable
2MUXOUT_SELR/W1Signal at MUXOUT pin
1: Lock Detect (3.3 V if locked, 0 V if unlocked)
0: Readback (3.3-V digital output)
1RESETR/W0Reset
Write with a value of 1 to reset device (this register will self-switch back to 0)
0POWERDOWNR/W0Powerdown whole device
1: power down
0: power up
Table 7-6 R1 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:3R/WProgram to Register Map default values
2:0CAL_CLK_DIVR/W3Divides down the OSCin signal for calibration clock
Calibration Clock = OSCin / 2^CAL_CLK_DIV
Set this value so that calibration clock is less than but as close to 200MHz as possible if fast calibration time is desired.
Table 7-7 R2 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-8 R4 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:8ACAL_CMP_DLYR/W25VCO amplitude calibration delay. Lowering this value can speed calibration time. The guideline for this register is 2 x [ACAL_CMP_DLY value] x [calibration clock period] > 200ns. As described in CAL_CLK_DIV, the calibration clock is defined as OSCin / 2^CAL_CLK_DIV. For example, with the fastest calibration clock of 200MHz (OSCin=200MHz and CAL_CLK_DIV=0), the period is 5ns. So ACAL_CMP_DLY should be > 20. With the same derivation, an example of a OSCin=100MHz, ACAL_CMP_DLY should be > 10. This register is left at a default value of 25 if there is no need to shorten calibration time.
7:0R/WProgram to Register Map default values
Table 7-9 R7 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-10 R8 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:14R/WProgram to Register Map default values
13VCO_IDAC_OVRR/W0This is the override bit for VCO amplitude (or IDAC value). When this is enabled, the VCO amplitude calibration function (ACAL_EN) is not used. VCO_IDAC register can be programmed to set the amplitude. Keep the VCO_IDAC value within 250 and 450.
12:11R/WProgram to Register Map default values
10VCO_CAPCTRL_OVRR/W0This is the override bit for VCO capacitor bank code (or CAPCTRL value). When this is enabled, the VCO frequency calibration function (FCAL_EN) is not used. the VCO_CAPCTRL register can be programmed to set the VCO frequency within the selected VCO core. The VCO core is selected by setting VCO_SEL_FORCE=1 and then selecting the core with VCO_SEL=1,2,3,4,5,6, or 7
9:0R/WProgram to Register Map default values
Table 7-11 R9 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11OSC_2XR/W0Reference path doubler
1: enable
0: disable
10R/WProgram to Register Map default values
9REF_ENR/W1Enable reference path
1: enable
0: disable
8:0R/WProgram to Register Map default values
Table 7-12 R10 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11:7MULTR/W1Input signal path multiplier (input range from 40 - 70 MHz, output range from 180 - 250 MHz)
6:0R/WProgram to Register Map default values
Table 7-13 R11 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11:4PLL_RR/W1R divider after multiplier and before PFD
3:0R/WProgram to Register Map default values
Table 7-14 R12 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11:0PLL_R_PRER/W1R divider after OSCin doubler and before multiplier
Table 7-15 R13 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15R/WProgram to Register Map default values
14CP_ENR/W1Enable charge pump
1: enable
0: disable
13:2R/WProgram to Register Map default values
1:0PFD_CTLR/W0PFD mode
0: Dual PFD (default)
3: Single PFD (ONLY use if PFD freq is higher than 200MHz)
Table 7-16 R14 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11:7CP_IDNR/W3Charge pump current (DN) – must equal to charge pump current (UP). Can activate any combination of bits.
<bit 4>: 1.25 mA
<bit 3>: 2.5 mA
<bit 2>: 0.625 mA
<bit 1>: 0.312 mA
<bit 0>: 0.156 mA
6:2CP_IUPR/W3Charge pump current (UP) – must equal to charge pump current (DN). Can activate any combination of bits.
<bit 4>: 1.25 mA
<bit 3>: 2.5 mA
<bit 2>: 0.625 mA
<bit 1>: 0.312 mA
<bit 0>: 0.156 mA
1:0CP_ICOARSER/W1Charge pump gain multiplier - multiplies charge pump current by a given factor:
3: multiply by 2.5
2: multiply by 1.5
1: multiply by 2
0: no multiplication
For optimal accuracy of the lock detect circuit over temperature, it is recommended that only set this register to either 0 or 2.
Table 7-17 R19 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11:3VCO_IDACR/W300This is the VCO amplitude (or IDAC value). When VCO_IDAC is overridden with VCO_IDAC_OVR=1, VCO amplitude calibration function (ACAL_EN) is not used. VCO_IDAC register can be programmed to set the amplitude. VCO_IDAC value must be kept within 250 and 450.
2:0R/WProgram to Register Map default values
Table 7-18 R20 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:9R/WProgram to Register Map default values
8:0ACAL_VCO_IDAC_STRTR/W300This register is used to aid the VCO amplitude calibration function (ACAL_EN). By default the amplitude calibration function searches from the low end of VCO_IDAC until it reaches the target value. Like the VCO_IDAC, this must be kept within 250 and 450. This can be set to a value closer to the target value, then the amplitude calibration time can be shortened typically final VCO_IDAC is somewhere around 300.
Table 7-19 R22 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:8R/WProgram to Register Map default values
7:0VCO_CAPCTRLR/W0This is the VCO capacitor bank code (or CAPCTRL value). When VCO_CAPCTRL is overridden with VCO_CAPCTRL_OVR=1, VCO frequency calibration function (FCAL_EN) is not used. VCO_CAPCTRL register can be programmed to set the frequency in that core. VCO_SEL_FORCE=1 has to be set and VCO_SEL to select the VCO core, then CAPCTRL values between 0 to 183 will produce frequencies within this core (0 being the highest frequency and 183 the lowest).
Table 7-20 R23 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15R/WProgram to Register Map default values
14FCAL_VCO_SEL_STRTR/W0This is a register that aids the frequency calibration function. When this is enabled, a VCO core can be selected for the frequency calibration to start at, set by register VCO_SEL. By default the frequency calibration starts from VCO core 7 and works its way down. If you want for example to lock to a frequency in VCO core 1, you can set VCO_SEL to 2, so the calibration will start at VCO core 2 and end at target frequency at VCO core 1 faster.
13:11VCO_SELR/W1This is the register used to select VCO cores. It works for VCO_CAPCTRL when VCO_CAPCTRL_OVR=1 and VCO_SEL_FORCE=1. It also aids the frequency calibration function with FCAL_VCO_SEL_STRT.
10VCO_SEL_FORCER/W0This register works to force selection of VCO cores. If VCO_CAPTRL_OVR=1 and this register is enabled, you can select the VCO core to use with VCO_SEL.
9:0R/WProgram to Register Map default values
Table 7-21 R24 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to default
Table 7-22 R25 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-23 R28 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-24 R29 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-25 R30 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:11R/WProgram to Register Map default values
10MASH_DITHERR/W0MASH dithering: toggle on/off to randomize
9:8 R/W Program to Register Map default values
7:6 VTUNE_ADJ R/W Change this register field according to the VCO frequency
0: fVCO < 6500 MHz
3: fVCO ≥ 6500 MHz
5:0 R/W Program to Register Map default values
Table 7-26 R31 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:11R/WProgram to Register Map default values
10VCO_DISTB_PDR/W1Power down buffer between VCO and output B
1: power down
0: power up
9VCO_DISTA_PDR/W0Power down buffer between VCO and output A
1: power down
0: power up
8R/WProgram to Register Map default values
7CHDIV_DIST_PDR/W0Power down buffer between VCO and channel divider
6:0R/WProgram to Register Map default values
Table 7-27 R32 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-28 R33 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-29 R34 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:6R/WProgram to Register Map default values
5CHDIV_ENR/W1Enable entire channel divider
1: enable
0: power down
4:0R/WProgram to Register Map default values
Table 7-30 R35 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:13R/WProgram to Register Map default values
12:9CHDIV_SEG2R/W1Channel divider segment 2
8: divide-by-8
4: divide-by-6
2: divide-by-4
1: divide-by-2
0: PD
8CHDIV_SEG3_ENR/W0Channel divider segment 3
1: enable
0: power down (power down if not needed)
7CHDIV_SEG2_ENR/W0Channel divider segment 2
1: enable
0: power down (power down if not needed)
6:3R/WProgram to Register Map default values
2CHDIV_SEG1R/W1Channel divider segment 1
1: divide-by-3
0: divide-by-2
1CHDIV_SEG1_ENR/W0Channel divider segment 1
1: enable
0: power down (power down if not needed)
0R/WProgram to Register Map default values
Table 7-31 R36 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:12R/WProgram to Register Map default values
11CHDIV_DISTB_ENR/W0Enable buffer between channel divider and output B
1: enable
0: disable
10CHDIV_DISTA_ENR/W1Enable buffer between channel divider and output A
1: enable
0: disable
9:7R/WProgram to Register Map default values
6:4CHDIV_SEG_SELR/W1Channel divider segment select
4: includes channel divider segment 1,2 and 3
2: includes channel divider segment 1 and 2
1: includes channel divider segment 1
0: PD
3:0CHDIV_SEG3R/W1Channel divider segment 3
8: divide-by-8
4: divide-by-6
2: divide-by-4
1: divide-by-2
0: PD
Table 7-32 R37 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:13R/WProgram to Register Map default values
12PLL_N_PRER/W0N-divider pre-scalar
1: divide-by-4
0: divide-by-2
11:0R/WProgram to Register Map default values
Table 7-33 R38 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:13R/WProgram to Register Map default values
12:1PLL_NR/W27Integer part of N-divider
0R/WProgram to Register Map default values
Table 7-34 R39 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:14R/WProgram to Register Map default values
13:8PFD_DLYR/W2PFD Delay
32: Not used
16: 16 clock cycle delay
8: 12 clock cycle delay
4: 8 clock cycle delay
2: 6 clock cycle delay
1: 4 clock cycle delay
7:0R/WProgram to Register Map default values
Table 7-35 R40 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0PLL_DEN[31:16]R/W1000Denominator MSB of N-divider fraction
Table 7-36 R41 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0PLL_DEN[15:0]R/W1000Denominator LSB of N-divider fraction
Table 7-37 R42 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0MASH_SEED[31:16]R/W0MASH seed MSB
Table 7-38 R43 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0MASH_SEED[15:0]R/W0MASH seed LSB
Table 7-39 R44 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0PLL_NUM[31:16]R/W0Numerator MSB of N-divider fraction
Table 7-40 R45 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0PLL_NUM[15:0]R/W0Numerator LSB of N-divider fraction
Table 7-41 R46 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15R/WProgram to Register Map default values
13:8OUTA_POWR/W15Output buffer A power
increase power from 0 to 31
extra boost from 48 to 63
7OUTB_PDR/W1Output buffer B power down
1: power down
0: power up
6OUTA_PDR/W0Output buffer A power down
1: power down
0: power up
5:3R/WProgram to Register Map default values
2:0MASH_ORDERR/W3Sigma-delta modulator order
4: fourth order
3: third order
2: second order
1: first order
0: integer mode
Table 7-42 R47 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:13R/WProgram to Register Map default values
12:11OUTA_MUXR/W0Selects signal to the output buffer
2,3: reserved
1: Selects output from VCO
0: Selects the channel divider output
10:6R/WProgram to Register Map default values
5:0OUTB_POWR/W0Output buffer B power
increase power from 0 to 31
extra boost from 48 to 63
Table 7-43 R48 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:2R/WProgram to Register Map default values
1:0OUTB_MUXR/W0Selects signal to the output buffer
2,3: reserved
1: Selects output from VCO
0: Selects the channel divider output
Table 7-44 R59 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:6R/WProgram to Register Map default values
5MUXOUT_HDRVR/W0This bit enables higher current output (approximately 3 mA) at MUXOUT pin if value is 1.
4:0R/WProgram to Register Map default values
Table 7-45 R61 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:1R/WProgram to Register Map default values
0LD_TYPER/W1To use lock detect, set MUXOUT_SEL=1. Use this register to select type of lock detect:
0: Calibration status detect (this indicates if the auto-calibration process has completed successfully and will output from MUXout pin a logic HIGH when successful). 1: vtune detect (this checks if vtune is in the expected range of voltages and outputs from MUXout pin a logic HIGH if device is locked and LOW if unlocked).
Table 7-46 R62 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:0R/WProgram to Register Map default values
Table 7-47 R64 Register Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15:10R/WProgram to Register Map default values
9ACAL_FASTR/W0Enable fast amplitude calibration
1: enable
0: disable
8FCAL_FASTR/W0Enable fast frequency calibration
1: enable
0: disable
7:5AJUMP_SIZER/W3When ACAL_FAST=1, use this register to select the jump increment
4R/WProgram to Register Map default values
3:0FJUMP_SIZER/W15When FCAL_FAST=1, use this register to select the jump increment
Table 7-48 R68 Register Field Descriptions
BIT FIELD TYPE DEFAULT DESCRIPTION
10:9 rb_LD_VTUNE R – Readback of Vtune detect (LD_TYPE = 1).
0: Unlocked
1: Invalid
2: Locked
3: Unlocked
7:5 rb_VCO_SEL R – Reads back the actual VCO that the calibration has selected.
1: VCO1
2: VCO2
……
7: VCO7
Table 7-49 R69 Register Field Descriptions
BIT FIELD TYPE DEFAULT DESCRIPTION
7:0 rb_VCO_CAPCTRL R – Reads back the actual CAPCTRL value that the VCO calibration has chosen.
Table 7-50 R70 Register Field Descriptions
BIT FIELD TYPE DEFAULT DESCRIPTION
8:0 rb_VCO_DACISET R - Reads back the actual DACISET value that the VCO calibration has chosen.