SNAS680E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

8.1.1.2 Spur Mitigation Techniques

Once the spur is identified and understood, there will likely be a desire to try to minimize them. 8-2 gives some common methods.

Table 8-2 Spurs and Mitigation Techniques
SPUR TYPEWAYS TO REDUCETRADE-OFF
OSCin
  1. Use PLL_N_PRE = 2
  2. Use an OSCin signal with low amplitude and high slew rate (like LVDS).
Phase Detector
  1. Decrease PFD_DLY
  2. To pin 11, use a series ferrite bead and a shunt 0.1-µF capacitor.
fOUT % fOSCUse an OSCin signal with low amplitude and high slew rate (like LVDS)
fVCO% fOSC
  1. To pin 7, use a series ferrite bead and a shunt 0.1-µF capacitor.
  2. Increase the offset of this spur by shifting the VCO frequency
  3. If multiple VCO frequencies are possible that yield the same spur offset, choose the higher VCO frequency.
.
fVCO% fPDAvoid this spur by shifting the phase detector frequency (with the programmable input multiplier or R divider) or shifting the VCO frequency. This spur is better at higher VCO frequency.
Integer Boundary

Methods for PLL Dominated Spurs

  1. Avoid the worst case VCO frequencies if possible.
  2. Strategically choose which VCO core to use if possible.
  3. Ensure good slew rate and signal integrity at the OSCin pin
  4. Reduce the loop bandwidth or add more filter poles for out of band spurs
  5. Experiment with modulator order and PFD_DLY
Reducing the loop bandwidth may degrade the total integrated noise if the bandwidth is too narrow.

Methods for VCO Dominated Spurs

  1. Avoid the worst case VCO frequencies if possible.
  2. Reduce Phase Detector Frequency
  3. Ensure good slew rate and signal integrity at the OSCin pin
  4. Make the impedance looking outwards from the OSCin pin close to 50 Ω.
Reducing the phase detector may degrade the phase noise and also reduce the capacitance at the Vtune pin.
Primary Fractional
  1. Decrease Loop Bandwidth
  2. Change Modulator Order
  3. Use Larger Unequivalent Fractions
Decreasing the loop bandwidth too much may degrade in-band phase noise. Also, larger unequivalent fractions only sometimes work
Sub-Fractional
  1. Use Dithering
  2. Use MASH seed
  3. Use Larger Equivalent Fractions
  4. Use Larger Unequivalent Fractions
  5. Reduce Modulator Order
  6. Eliminate factors of 2 or 3 in denominator (see AN-1879 Fractional N Frequency Synthesis (SNAA062)
Dithering and larger fractions may increase phase noise. MASH_SEED can be set between values 0 and Fden, which changes the sub-fractional spur behavior. This is a deterministic relationship and there will be one seed value that will give best result for this spur.