SNAS692A January   2017  – May 2017 LMK61E0M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  3.3-V LVCMOS Output Characteristics
    7. 6.7  OE Input Characteristics
    8. 6.8  ADD Input Characteristics
    9. 6.9  Frequency Tolerance Characteristics
    10. 6.10 Frequency Margining Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 I2C-Compatible Interface Characteristics (SDA, SCL)
    13. 6.13 Other Characteristics
    14. 6.14 PLL Clock Output Jitter Characteristics
    15. 6.15 Additional Reliability and Qualification
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Divider and Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Engine
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
      2. 8.4.2 DCXO Mode and Frequency Margining
        1. 8.4.2.1 DCXO Mode
        2. 8.4.2.2 Fine Frequency Margining
        3. 8.4.2.3 Coarse Frequency Margining
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  VNDRID_BY1 Register; R0
        2. 8.6.1.2  VNDRID_BY0 Register; R1
        3. 8.6.1.3  PRODID Register; R2
        4. 8.6.1.4  REVID Register; R3
        5. 8.6.1.5  SLAVEADR Register; R8
        6. 8.6.1.6  EEREV Register; R9
        7. 8.6.1.7  DEV_CTL Register; R10
        8. 8.6.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.6.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.6.1.10 CMOSCTL Register; R20
        11. 8.6.1.11 DIFFCTL Register; R21
        12. 8.6.1.12 OUTDIV_BY1 Register; R22
        13. 8.6.1.13 OUTDIV_BY0 Register; R23
        14. 8.6.1.14 RDIVCMOSCTL Register; R24
        15. 8.6.1.15 PLL_NDIV_BY1 Register; R25
        16. 8.6.1.16 PLL_NDIV_BY0 Register; R26
        17. 8.6.1.17 PLL_FRACNUM_BY2 Register; R27
        18. 8.6.1.18 PLL_FRACNUM_BY1 Register; R28
        19. 8.6.1.19 PLL_FRACNUM_BY0 Register; R29
        20. 8.6.1.20 PLL_FRACDEN_BY2 Register; R30
        21. 8.6.1.21 PLL_FRACDEN_BY1 Register; R31
        22. 8.6.1.22 PLL_FRACDEN_BY0 Register; R32
        23. 8.6.1.23 PLL_MASHCTRL Register; R33
        24. 8.6.1.24 PLL_CTRL0 Register; R34
        25. 8.6.1.25 PLL_CTRL1 Register; R35
        26. 8.6.1.26 PLL_LF_R2 Register; R36
        27. 8.6.1.27 PLL_LF_C1 Register; R37
        28. 8.6.1.28 PLL_LF_R3 Register; R38
        29. 8.6.1.29 PLL_LF_C3 Register; R39
        30. 8.6.1.30 PLL_CALCTRL Register; R42
        31. 8.6.1.31 NVMSCRC Register; R47
        32. 8.6.1.32 NVMCNT Register; R48
        33. 8.6.1.33 NVMCTL Register; R49
        34. 8.6.1.34 MEMADR Register; R51
        35. 8.6.1.35 NVMDAT Register; R52
        36. 8.6.1.36 RAMDAT Register; R53
        37. 8.6.1.37 NVMUNLK Register; R56
        38. 8.6.1.38 INT_LIVE Register; R66
        39. 8.6.1.39 SWRST Register; R72
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PLL Loop Filter Design
        2. 9.2.2.2 Spur Mitigation Techniques
          1. 9.2.2.2.1 Phase Detection Spur
          2. 9.2.2.2.2 Integer Boundary Fractional Spur
          3. 9.2.2.2.3 Primary Fractional Spur
          4. 9.2.2.2.4 Sub-Fractional Spur
        3. 9.2.2.3 Device Programming
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

1 Features

  • Ultra-Low Noise, High Performance
    • Jitter: 500-fs RMS Typical fOUT > 50 MHz on LMK61E0M
  • LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
  • Default Frequency: 70.656 MHz

2 Applications

  • High-Performance Replacement for Crystal, SAW, or Silicon-Based Oscillators
  • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
  • Test and Measurement
  • Medical Imaging
  • FPGA, Processor Attach
  • xDSL, Broadcast Video

3 Description

The LMK61E0 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMK61E0M QFM (8) 7.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Pinout and Simplified Block Diagram

LMK61E0M pinout_functional_block_diagram_snas692.gif