SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The CLKIN_CTRL1 Register provides control of CLK Input features. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7] | CLKINBLK_ALL_EN | RW | 0 | CLK Inputs All Enabled after Clock Switch. If CLKINBLK_ALL_EN is 1 then all clock input paths remain enabled after a valid clock has been selected. If CLKINBLK_ALL_EN is 0 then the clock paths are disabled apart from the selected clock. |
[6:5] | CLKINSEL1_MODE[1:0] | RW | 0x0 | CLK Input Select Mode.
CLKINSEL1_MODE– CLOCK Selection Mode 0– Auto 1– Pin 2– Register |
[4] | CLKINBLK_EN_BUF_CLK_PLL | RW | 0 | Clock Buffer for PLL1 Enable. |
[3] | CLKINBLK_EN_BUF_BYP_PLL | RW | 0 | Clock Buffer for PLL2 Enable (PLL1 By-Passed). |
[2] | RSRVD | RW | 0 | Reserved. |
[1] | RSRVD | RW | 0 | Reserved. |
[0] | RSRVD | RW | 0 | Reserved. |