SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The CLKIN1CTRL Register provides control of the CLK1 input path. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7] | RSRVD | - | - | Reserved. |
[6] | CLKIN1_PLL1_INV | RW | 1 | Inverts CLKIN1_PLL1_RDIV.
0=Non-Inverted 1=Inverted |
[5] | CLKIN1_LOS_FRQ_DBL_EN | RW | 0 | CLKIN1 Loss of Source Frequency Doubler Enable. |
[4] | CLKIN1_EN | RW | 0 | CLKIN1 Input Stage Enable. (not CLK buffer). |
[3] | CLKIN1_SE_MODE | RW | 1 | CLKIN1 Signal Mode.
CLKIN1_SE_MODE– Signal Mode Selection 0– Differential 1– Single-ended |
[2:0] | CLKIN1_PRIO[2:0] | RW | 0x4 | CLKIN1 Priority.
CLKIN1_PRIO– Clock Priority 0– Clock Disabled 1– Priority 1– Highest 2– Priority 2 3– Priority 3 4– Priority 4– Lowest |