SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
Two status pins are available (STATUS0, STATUS1). STATUSx/SYNC_OUTPUT_HIZ = 1 configures the pins as input, while STATUSx/SYNC_OUTPUT_HIZ = 0 configures the pins as output. STATUSx/SYNC_INT_MUX register configures the pin functions in Table 10.
FUNCTION | INPUT/OUTPUT | DESCRIPTION |
---|---|---|
SDO | Output | Serial Data Output for 4-wire SPI |
LD1 and LD2 | Output | Digital Lock Detect for PLL1 and PLL2 |
LD1 | Output | Digital Lock Detect for PLL1 |
LD2 | Output | Digital Lock Detect for PLL2 |
LD1 and LD2 and not Holdover | Output | PLL1 Lock Detect and PLL2 Lock Detect and not PLL1 Holdover |
LD1 and not Holdover | Output | PLL1 Lock Detect and not PLL1 Holdover |
LOS | Output | Output of LOS Block |
Holdover status | Output | Output of Holdover Status. High = Holdover. Low = Normal operation |
Holdover Control | Input | Manual Holdover entry through pin. See Holdover. |
Copy SYNC pin | Output | Outputs a copy of SYNC pin |
Copy CLKIN_SEL pin | Output | Outputs a copy of CLKIN_SEL pin |
PLL2 Reference Clock | Output | PLL2 Reference Clock (Copy of OSCin divided by PLL2 R) |
PLL1_R | Output | Output PLL1_R Clock Frequency |
PLL2_R | Output | Output PLL2_R Clock Frequency |
PLL1_N | Output | Output PLL1_N Clock Frequency |
PLL2_N | Output | Output PLL2_N Clock Frequency |
Logic High | Output | |
Logic Low | Output |