SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The DIGCLKCTRL Register allows control of the digital system clock. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:3] | RSRVD | - | - | Reserved. |
[2] | DIG_CLK_EN | RW | 1 | Digital Clock Enable. When DIG_CLK_EN is 1 the digital system clock is active. When DIG_CLK_EN is 0 the digital system clock is disabled. |
[1] | PLL2_DIG_CLK_EN | RW | 1 | Enable PLL2 Digital Clock Buffer. |
[0] | PORCLKAFTERLOCK | RW | 0 | POR Clock behavior after Lock. If PORCLKAFTERLOCK is 0 then the system clock is switched from the POR Clock to the PLL2 Digital Clock after lock and the POR Clock oscillator is disabled. If PORCLKAFTERLOCK is 1, the POR Clock remains as the digital system clock regardless of the PLL Lock state. |