SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
L(f)CLKout/OSCoutNF | Noise floor
20-MHz offset ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2(1) |
122.88 MHz | HSDS 4 mA | –166 | dBc/Hz | ||
HSDS 6 mA | –166 | ||||||
HSDS 8 mA | –166 | ||||||
HCSL 16 mA | –165 | ||||||
OSCout, HSDS 4 mA | –161 | ||||||
OSCout, HSDS 8 mA | –161 | ||||||
OSCout, LVCMOS | –156 | ||||||
L(f)CLKoutNF,ADLY | Noise floor with analog delay enabled
20-MHz offset ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2(1) |
122.88 MHz, maximum analog delay setting | HSDS 4 mA | –151 | dBc/Hz | ||
HSDS 6 mA | –151 | ||||||
HSDS 8 mA | –151 | ||||||
HCSL 16 mA | –151 | ||||||
L(f)CLKoutPN | SSB phase noise(3)
122.88-MHz output frequency ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2 (1)(2) |
Offset = 100 Hz | –97 | dBc/Hz | |||
Offset = 1 kHz | –126 | ||||||
Offset = 10 kHz | –139 | ||||||
Offset = 100 kHz | –147 | ||||||
Offset = 800 kHz | –158 | ||||||
Offset = 1 MHz | –159 | ||||||
Offset = 10 MHz | HSDS 8 mA | –166 | |||||
HCSL 16 mA | –165 | ||||||
L(f)OSCoutPN | SSB phase noise
122.88-MHz output frequency ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2 (1)(2) |
Offset = 100 Hz | –97 | dBc/Hz | |||
Offset = 1 kHz | –136 | ||||||
Offset = 10 kHz | –148 | ||||||
Offset = 100 kHz | –157 | ||||||
Offset = 1 MHz | HSDS 4 mA | –160 | |||||
Offset = 10 MHz | HSDS 8 mA | –160 | |||||
JCLKout | fCLKout = 122.88 MHz
Integrated RMS jitter ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2 (1)(4) |
HSDS 8 mA, BW = 100 Hz to 20 MHz | 160 | fs rms | |||
HSDS 8 mA, BW = 10 kHz to 20 MHz | 75 | ||||||
HCSL 16 mA, BW = 100 Hz to 20 MHz | 160 | ||||||
HCSL 16 mA, BW = 10 kHz to 20 MHz | 75 |