SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The PLL1_HOLDOVER_CTRL0 Register selects the GPIO pin to use to force Holdover mode. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:4] | RSRVD | - | - | Reserved. |
[3] | PLL1_CLKINSEL1_ML_HOLDOVER | RW | 0 | Force holdover by applying mid-level at CLKINSEL1. |
[2] | PLL1_SYNC_HOLDOVER | RW | 0 | Force holdover by applying high-level at SYNC. |
[1] | PLL1_STATUS1_HOLDOVER | RW | 0 | Force holdover by applying high-level at STATUS1. |
[0] | PLL1_STATUS0_HOLDOVER | RW | 0 | Force holdover by applying high-level at STATUS0. |