SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
PLL1 bandwidth can be increased or decreased even further by using the different PROP modes (see Table 14).
In the default input mode, the proportional is effective for 50% of the PFD clock period. Using low pulse mode, the effect of the proportional is reduced which results in a reduced PLL bandwidth. Similarly, using the high pulse mode, the proportional is effective for more than half of the PFD cycle, which results in higher bandwidth.
PLL1_INTG settings affect the integral gain in the loop. TI recommends using setting 0 in normal mode and higher settings only for Fast lock using PLL1_INTG_FL.