SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The PLL1CTRL0 Register provides control of the following PLL1 related features. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7] | PLL1_F_30 | RW | 0 | PLL1 RC Freq 0=122MHz 1=32MHz.
PLL1_F_30– PLL1 RC Frequency 0– 122MHz 1– 32MHz |
[6] | PLL1_EN_REGULATION | RW | 0 | PLL1 Prop-CP Enable Regulation |
[5] | PLL1_PD_LD | RW | 1 | PLL1 Window Comparator Power Down.
PLL1_PD_LD– PLL1 Window Comparator 0– Enabled 1– Off |
[4] | PLL1_DIR_POS_GAIN | RW | 1 | PLL1 VCXO pos/neg Gain.
PLL1_DIR_POS_GAIN– Polarity 0– Positive 1– Negative |
[3:0] | PLL1_LDO_WAIT_TMR[3:0] | RW | 0x0 | PLL1 LDO Wait Timer. The PLL1 LDO Wait Timer counts a number of clock cycles equal to 32*(PLL1_LDO_WAIT_TMR+31) before releasing the PLL1 NDIV and RDIV resets. |