SNAS699B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The PLL1CTRL2 Register provides control over PLL1 related features. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:5] | RSRVD | - | - | Reserved. |
[4] | PLL1_LOL_NORESET | RW | 0 | If set to 1, PLL1 will not reset on a Loss-of-Lock event. |
[3] | PLL1_RDIV_CLKEN | RW | 1 | PLL1 RDIV Clock Enable. |
[2] | PLL1_RDIV_4CY | RW | 1 | PLL1 RDIV Enable tied clock low phase to 4cycs. Independent from divider setting. |
[1] | PLL1_NDIV_CLKEN | RW | 1 | PLL1 NDIV Clock Enable |
[0] | PLL1_NDIV_4CY | RW | 1 | PLL1 NDIV Enable tied clock low phase to 4cycs. Independent from divider setting. |