SNAS699B January   2017  – July 2019 LMK04610

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: LMK04610
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
    6. 7.6  Clock Input Characteristics (CLKinX)
    7. 7.7  Clock Input Characteristics (OSCin)
    8. 7.8  PLL1 Specification Characteristics
    9. 7.9  PLL2 Specification Characteristics
    10. 7.10 Clock Output Type Characteristics (CLKoutX)
    11. 7.11 Oscillator Output Characteristics (OSCout)
    12. 7.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
    13. 7.13 Clock Output Skew and Isolation Characteristics
    14. 7.14 Clock Output Delay Characteristics
    15. 7.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
    16. 7.16 Power Supply Characteristics
    17. 7.17 Typical Power Supply Noise Rejection Characteristics
    18. 7.18 SPI Interface Timing
    19. 7.19 Timing Diagram
    20. 7.20 Typical Characteristics
      1. 7.20.1 Clock Output AC Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
    2. 8.2 Output Termination Scheme
      1. 8.2.1 HSDS 4/6/8mA
      2. 8.2.2 HCSL
      3. 8.2.3 LVCMOS
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Jitter Cleaning
      2. 9.1.2 Two Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
      3. 9.1.3 VCXO Buffered Output
      4. 9.1.4 Frequency Holdover
      5. 9.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
      6. 9.1.6 Internal VCOs
      7. 9.1.7 Clock Distribution
        1. 9.1.7.1 Output Clock Divider
        2. 9.1.7.2 Output Clock Delay
        3. 9.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
        4. 9.1.7.4 Programmable Output Formats
        5. 9.1.7.5 Clock Output SYNChronization
      8. 9.1.8 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
        1. 9.3.1.1 Input Clock Switching
          1. 9.3.1.1.1 Input Clock Switching – Register Select Mode
          2. 9.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL)
          3. 9.3.1.1.3 Input Clock Switching – Automatic Mode
        2. 9.3.1.2 Loss of Signal Detection – LOS
          1. 9.3.1.2.1 LOS – Assertion
          2. 9.3.1.2.2 LOS – Reference Clock Recovery
        3. 9.3.1.3 Driving CLKin and OSCin Inputs
          1. 9.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
          2. 9.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
      2. 9.3.2 Clock Outputs (CLKoutX)
        1. 9.3.2.1 HCSL
        2. 9.3.2.2 HSDS
        3. 9.3.2.3 SYNC
        4. 9.3.2.4 Digital Delay
          1. 9.3.2.4.1 Fixed Digital Delay
          2. 9.3.2.4.2 Dynamic Digital Delay
        5. 9.3.2.5 Analog Delay
      3. 9.3.3 OSCout
        1. 9.3.3.1 Pin-Controlled OSCout Divider
      4. 9.3.4 STATUS0/1 and SYNC Pin Functions
        1. 9.3.4.1 Common STATUS0/1 and SYNC Pin Functions
        2. 9.3.4.2 Additional STATUS0 Pin Functions
        3. 9.3.4.3 Additional SYNC Pin Functions
      5. 9.3.5 PLL1 and PLL2
        1. 9.3.5.1 PLL1
          1. 9.3.5.1.1 PLL1 Proportional Modes
          2. 9.3.5.1.2 PLL1 Higher Order Poles
        2. 9.3.5.2 PLL2
          1. 9.3.5.2.1 PLL2 Divider
          2. 9.3.5.2.2 PLL2 Input Modes
          3. 9.3.5.2.3 PLL2 Loop Filter
          4. 9.3.5.2.4 PLL2 3rd Order Loop Filter
          5. 9.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
          6. 9.3.5.2.6 Examples of PLL2 Setting
        3. 9.3.5.3 Digital Lock Detect
          1. 9.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
      6. 9.3.6 Holdover
        1. 9.3.6.1 Holdover Flowchart
        2. 9.3.6.2 Enable Holdover
          1. 9.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
        3. 9.3.6.3 Enter Holdover
          1. 9.3.6.3.1 LOS_x Detect
          2. 9.3.6.3.2 PLL1 DLD Detect
          3. 9.3.6.3.3 CTRL_VCXO Rail Detect
            1. 9.3.6.3.3.1 Absolute Limits
            2. 9.3.6.3.3.2 Relative Limits
          4. 9.3.6.3.4 Manual Holdover Enable – Register Control
          5. 9.3.6.3.5 Manual Holdover Enable – Pin Control
          6. 9.3.6.3.6 Start-Up into Holdover
        4. 9.3.6.4 During Holdover
        5. 9.3.6.5 Exiting Holdover
        6. 9.3.6.6 Holdover Frequency Accuracy
        7. 9.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
        8. 9.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
      7. 9.3.7 JEDEC JESD204B
        1. 9.3.7.1 SYNC Pins
        2. 9.3.7.2 SYNC modes
        3. 9.3.7.3 SYSREF Modes
          1. 9.3.7.3.1 SYSREF Pulser
            1. 9.3.7.3.1.1 SPI Pulser Mode
            2. 9.3.7.3.1.2 Pin Pulser Mode
            3. 9.3.7.3.1.3 Multiple SYSREF Frequencies
          2. 9.3.7.3.2 Continuous SYSREF
          3. 9.3.7.3.3 SYSREF Request
        4. 9.3.7.4 How to Enable SYSREF
          1. 9.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
          2. 9.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
      8. 9.3.8 Zero Delay Mode (ZDM)
      9. 9.3.9 Power-Up Sequence
    4. 9.4 Device Functional Modes
      1. 9.4.1 Dual PLL
      2. 9.4.2 Single PLL
      3. 9.4.3 PLL2 Bypass
      4. 9.4.4 Clock Distribution
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 Readback
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
      2. 9.6.2 Device Register Descriptions
        1. 9.6.2.1   CONFIGA
        2. 9.6.2.2   RESERVED1
        3. 9.6.2.3   RESERVED2
        4. 9.6.2.4   CHIP_TYPE
        5. 9.6.2.5   CHIP_ID_BY1
        6. 9.6.2.6   CHIP_ID_BY0
        7. 9.6.2.7   CHIP_VER
        8. 9.6.2.8   RESERVED3
        9. 9.6.2.9   RESERVED4
        10. 9.6.2.10  RESERVED5
        11. 9.6.2.11  RESERVED6
        12. 9.6.2.12  RESERVED7
        13. 9.6.2.13  VENDOR_ID_BY1
        14. 9.6.2.14  VENDOR_ID_BY0
        15. 9.6.2.15  RESERVED8
        16. 9.6.2.16  RESERVED9
        17. 9.6.2.17  STARTUP_CFG
        18. 9.6.2.18  STARTUP
        19. 9.6.2.19  DIGCLKCTRL
        20. 9.6.2.20  PLL2REFCLKDIV
        21. 9.6.2.21  GLBL_SYNC_SYSREF
        22. 9.6.2.22  CLKIN_CTRL0
        23. 9.6.2.23  CLKIN_CTRL1
        24. 9.6.2.24  CLKIN0CTRL
        25. 9.6.2.25  CLKIN1CTRL
        26. 9.6.2.26  CLKIN0RDIV_BY1
        27. 9.6.2.27  CLKIN0RDIV_BY0
        28. 9.6.2.28  CLKIN1RDIV_BY1
        29. 9.6.2.29  CLKIN1RDIV_BY0
        30. 9.6.2.30  CLKIN0LOS_REC_CNT
        31. 9.6.2.31  CLKIN0LOS_LAT_SEL
        32. 9.6.2.32  CLKIN1LOS_REC_CNT
        33. 9.6.2.33  CLKIN1LOS_LAT_SEL
        34. 9.6.2.34  CLKIN_SWCTRL0
        35. 9.6.2.35  CLKIN_SWCTRL1
        36. 9.6.2.36  CLKIN_SWCTRL2
        37. 9.6.2.37  OSCIN_CTRL
        38. 9.6.2.38  OSCOUT_CTRL
        39. 9.6.2.39  OSCOUT_DIV
        40. 9.6.2.40  OSCOUT_DRV
        41. 9.6.2.41  OUTCH_SWRST
        42. 9.6.2.42  OUTCH1CNTL0
        43. 9.6.2.43  OUTCH1CNTL1
        44. 9.6.2.44  OUTCH2CNTL0
        45. 9.6.2.45  OUTCH2CNTL1
        46. 9.6.2.46  OUTCH34CNTL0
        47. 9.6.2.47  OUTCH34CNTL1
        48. 9.6.2.48  OUTCH5CNTL0
        49. 9.6.2.49  OUTCH5CNTL1
        50. 9.6.2.50  OUTCH6CNTL0
        51. 9.6.2.51  OUTCH6CNTL1
        52. 9.6.2.52  OUTCH78CNTL0
        53. 9.6.2.53  OUTCH78CNTL1
        54. 9.6.2.54  OUTCH9CNTL0
        55. 9.6.2.55  OUTCH9CNTL1
        56. 9.6.2.56  OUTCH10CNTL0
        57. 9.6.2.57  OUTCH10CNTL1
        58. 9.6.2.58  OUTCH1DIV_BY1
        59. 9.6.2.59  OUTCH1DIV_BY0
        60. 9.6.2.60  OUTCH2DIV_BY1
        61. 9.6.2.61  OUTCH2DIV_BY0
        62. 9.6.2.62  OUTCH34DIV_BY1
        63. 9.6.2.63  OUTCH34DIV_BY0
        64. 9.6.2.64  OUTCH5DIV_BY1
        65. 9.6.2.65  OUTCH5DIV_BY0
        66. 9.6.2.66  OUTCH6DIV_BY1
        67. 9.6.2.67  OUTCH6DIV_BY0
        68. 9.6.2.68  OUTCH78DIV_BY1
        69. 9.6.2.69  OUTCH78DIV_BY0
        70. 9.6.2.70  OUTCH9DIV_BY1
        71. 9.6.2.71  OUTCH9DIV_BY0
        72. 9.6.2.72  OUTCH10DIV_BY1
        73. 9.6.2.73  OUTCH10DIV_BY0
        74. 9.6.2.74  OUTCH_DIV_INV
        75. 9.6.2.75  PLL1CTRL0
        76. 9.6.2.76  PLL1CTRL1
        77. 9.6.2.77  PLL1CTRL2
        78. 9.6.2.78  PLL1_SWRST
        79. 9.6.2.79  PLL1WNDWSIZE
        80. 9.6.2.80  PLL1STRCELL
        81. 9.6.2.81  PLL1CPSETTING
        82. 9.6.2.82  PLL1CPSETTING_FL
        83. 9.6.2.83  PLL1_HOLDOVER_CTRL1
        84. 9.6.2.84  PLL1_HOLDOVER_MAXCNT_BY3
        85. 9.6.2.85  PLL1_HOLDOVER_MAXCNT_BY2
        86. 9.6.2.86  PLL1_HOLDOVER_MAXCNT_BY1
        87. 9.6.2.87  PLL1_HOLDOVER_MAXCNT_BY0
        88. 9.6.2.88  PLL1_NDIV_BY1
        89. 9.6.2.89  PLL1_NDIV_BY0
        90. 9.6.2.90  PLL1_LOCKDET_CYC_CNT_BY2
        91. 9.6.2.91  PLL1_LOCKDET_CYC_CNT_BY1
        92. 9.6.2.92  PLL1_LOCKDET_CYC_CNT_BY0
        93. 9.6.2.93  PLL1_STRG_BY4
        94. 9.6.2.94  PLL1_STRG_BY3
        95. 9.6.2.95  PLL1_STRG_BY2
        96. 9.6.2.96  PLL1_STRG_BY1
        97. 9.6.2.97  PLL1_STRG_BY0
        98. 9.6.2.98  PLL1RCCLKDIV
        99. 9.6.2.99  PLL2_CTRL0
        100. 9.6.2.100 PLL2_CTRL1
        101. 9.6.2.101 PLL2_CTRL2
        102. 9.6.2.102 PLL2_SWRST
        103. 9.6.2.103 PLL2_LF_C4R4
        104. 9.6.2.104 PLL2_LF_C3R3
        105. 9.6.2.105 PLL2_CP_SETTING
        106. 9.6.2.106 PLL2_NDIV_BY1
        107. 9.6.2.107 PLL2_NDIV_BY0
        108. 9.6.2.108 PLL2_RDIV_BY1
        109. 9.6.2.109 PLL2_RDIV_BY0
        110. 9.6.2.110 PLL2_STRG_INIT_BY1
        111. 9.6.2.111 PLL2_STRG_INIT_BY0
        112. 9.6.2.112 RAILDET_UP
        113. 9.6.2.113 RAILDET_LOW
        114. 9.6.2.114 PLL2_AC_CTRL
        115. 9.6.2.115 PLL2_CURR_STOR_CELL
        116. 9.6.2.116 PLL2_AC_THRESHOLD
        117. 9.6.2.117 PLL2_AC_STRT_THRESHOLD
        118. 9.6.2.118 PLL2_AC_WAIT_CTRL
        119. 9.6.2.119 PLL2_AC_JUMPSTEP
        120. 9.6.2.120 PLL2_LD_WNDW_SIZE
        121. 9.6.2.121 PLL2_LD_WNDW_SIZE_INITIAL
        122. 9.6.2.122 PLL2_LOCKDET_CYC_CNT_BY2
        123. 9.6.2.123 PLL2_LOCKDET_CYC_CNT_BY1
        124. 9.6.2.124 PLL2_LOCKDET_CYC_CNT_BY0
        125. 9.6.2.125 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
        126. 9.6.2.126 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
        127. 9.6.2.127 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
        128. 9.6.2.128 IOCTRL_SPI0
        129. 9.6.2.129 IOCTRL_SPI1
        130. 9.6.2.130 IOTEST_SDIO
        131. 9.6.2.131 IOTEST_SCL
        132. 9.6.2.132 IOTEST_SCS
        133. 9.6.2.133 IOCTRL_STAT0
        134. 9.6.2.134 IOCTRL_STAT1
        135. 9.6.2.135 STAT1MUX
        136. 9.6.2.136 STAT0MUX
        137. 9.6.2.137 STATPLL2CLKDIV
        138. 9.6.2.138 IOTEST_STAT0
        139. 9.6.2.139 IOTEST_STAT1
        140. 9.6.2.140 IOCTRL_SYNC
        141. 9.6.2.141 DUMMY_REGISTER_1
        142. 9.6.2.142 IOCTRL_CLKINSEL1
        143. 9.6.2.143 IOTEST_CLKINSEL1
        144. 9.6.2.144 PLL1_TSTMODE
        145. 9.6.2.145 PLL2_CTRL
        146. 9.6.2.146 STATUS
        147. 9.6.2.147 PLL2_DLD_EN
        148. 9.6.2.148 PLL2_DUAL_LOOP
        149. 9.6.2.149 RESERVED10
        150. 9.6.2.150 CH1_DDLY_BY0
        151. 9.6.2.151 CH2_DDLY_BY0
        152. 9.6.2.152 CH34_DDLY_BY0
        153. 9.6.2.153 CH5_DDLY_BY0
        154. 9.6.2.154 CH6_DDLY_BY0
        155. 9.6.2.155 CH78_DDLY_BY0
        156. 9.6.2.156 CH9_DDLY_BY0
        157. 9.6.2.157 CH10_DDLY_BY0
        158. 9.6.2.158 OUTCH1_JESD_CTRL
        159. 9.6.2.159 OUTCH2_JESD_CTRL
        160. 9.6.2.160 OUTCH3_JESD_CTRL
        161. 9.6.2.161 OUTCH4_JESD_CTRL
        162. 9.6.2.162 OUTCH5_JESD_CTRL
        163. 9.6.2.163 OUTCH6_JESD_CTRL
        164. 9.6.2.164 OUTCH7_JESD_CTRL
        165. 9.6.2.165 OUTCH8_JESD_CTRL
        166. 9.6.2.166 OUTCH9_JESD_CTRL
        167. 9.6.2.167 OUTCH10_JESD_CTRL
        168. 9.6.2.168 CLKMUXVECTOR
        169. 9.6.2.169 OUTCH1CNTL2
        170. 9.6.2.170 OUTCH2CNTL2
        171. 9.6.2.171 OUTCH34CNTL2
        172. 9.6.2.172 OUTCH5CNTL2
        173. 9.6.2.173 OUTCH6CNTL2
        174. 9.6.2.174 OUTCH78CNTL2
        175. 9.6.2.175 OUTCH9CNTL2
        176. 9.6.2.176 OUTCH10CNTL2
        177. 9.6.2.177 OUTCH1_JESD_CTRL1
        178. 9.6.2.178 OUTCH2_JESD_CTRL1
        179. 9.6.2.179 OUTCH3_JESD_CTRL1
        180. 9.6.2.180 OUTCH4_JESD_CTRL1
        181. 9.6.2.181 OUTCH5_JESD_CTRL1
        182. 9.6.2.182 OUTCH6_JESD_CTRL1
        183. 9.6.2.183 OUTCH7_JESD_CTRL1
        184. 9.6.2.184 OUTCH8_JESD_CTRL1
        185. 9.6.2.185 OUTCH9_JESD_CTRL1
        186. 9.6.2.186 OUTCH10_JESD_CTRL1
        187. 9.6.2.187 SYSREF_PLS_CNT
        188. 9.6.2.188 SYNCMUX
        189. 9.6.2.189 IOTEST_SYNC
        190. 9.6.2.190 OUTCH_ZDM
        191. 9.6.2.191 PLL2_CTRL3
        192. 9.6.2.192 PLL1_HOLDOVER_CTRL0
        193. 9.6.2.193 IOCTRL_SYNC_1
        194. 9.6.2.194 OUTCH_TOP_JESD_CTRL
        195. 9.6.2.195 OUTCH_BOT_JESD_CTRL
        196. 9.6.2.196 OUTCH_JESD_CTRL1
        197. 9.6.2.197 PLL2_CTRL4
        198. 9.6.2.198 PLL2_CTRL5
        199. 9.6.2.199 PLL2_CTRL6
        200. 9.6.2.200 PLL2_CTRL7
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Lock Detect Frequency Accuracy
        1. 10.1.1.1 Minimum Lock Time Calculation Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PLL Loop Filter Design
        2. 10.2.2.2 Clock Output Assignment
        3. 10.2.2.3 Calculation Using LCM
        4. 10.2.2.4 Device Programming
        5. 10.2.2.5 Device Selection
        6. 10.2.2.6 Clock Architect
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Pin Connection Recommendations
  11. 11Power Supply Recommendations
    1. 11.1 Recommended Power Supply Connection
    2. 11.2 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 CLKin and OSCin
      2. 12.1.2 CLKout
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Clock Design Tool
        2. 13.1.1.2 Clock Architect
        3. 13.1.1.3 TICS Pro
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from A Revision (June 2017) to B Revision

  • Removed bulleted list under the Dual Loop PLL Architecture feature bulletGo
  • Added Ultra Low Noise feature bulletsGo
  • Changed VCO frequency units from: 5.8 to 6.175 GHz to: 5870 MHz to 6175 MHzGo
  • Added LMK04616 device configuration informationGo
  • Changed VCO frequency from: 5800 MHz to: 5870 MHzGo
  • Added PACKAGE column to device configuration information tableGo
  • Added LMK04616 row to device configuration information tableGo
  • Added Footnote and link to LMK04616 datasheet Go
  • Added OSCout polarity information to the OSCout/OSCout* pin descriptionGo
  • Changed PLL1 phase detector maximum frequency from 40 MHz to 4 MHz Go
  • Changed VCO tuning range minimum from: 5800 to: 5870Go
  • Changed VOD symbol to VOD,pp to match mVpp units.Go
  • Changed VOD symbol to VOD,pp to match mVpp units. Go
  • Added content to the HSDS 4/6/8mA section Go
  • Added content to the HCSL section Go
  • Changed the VCXO Buffered Output section Go
  • Changed VCO frequency to 5870 MHz to 6175 MHz and updated max output frequency to 2058 MHz Go
  • Added content to the Programmable Output Formats section Go
  • Changed HSDS to LVPECL With Bias Voltage Vb graphic captionGo
  • Changed HCSL to LVPECL graphicGo
  • Changed HSDS to LVPECL With Bias Voltage Vb graphic captionGo
  • Changed HSDS to LVPECL graphicGo
  • Added content to the OSCout section Go
  • Added OSCin to OSCout differential results in clock inversion from OSCin to OSCout. Go
  • Added Note to use TICS Pro EVM tool to calculate SDPLL loop filter values.Go
  • Changed PLL1_PROP max from 255 to 127. Go
  • Added PLL1_PROP_FL to table. Go
  • Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for Low Pulse modeGo
  • Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for High Pulse mode Go
  • Deleted Examples of PLL1 SettingGo
  • Changed the tuning range of the oscillator from: 5800 MHz to: 5870 MHzGo
  • Added PLL2 DLD programming information and updated the PLLx DLD flowchart graphic Go
  • Changed PLL1_STORAGE_CELL description from 40-bit thermometer code to 6-bit decimal value Go
  • Clarified CTRL_VCXO represented as PLL1_STORAGE_CELL value Go
  • Changed section from: Low Skew Mode to: Zero Delay Mode (ZDM) Go
  • Changed Set Prop/Store-CP from "fast lock" value to "non-fast lock" value at end of flowchartGo
  • Deleted references to tunable crystal Go
  • Deleted reference to CLKin2 and CLKin3 Go
  • Deleted use of external VCO for PLL2.Go
  • Added register 0x85, 0x86, 0xF6, and 0xAD for PLL2 DLD to recommended programming sequenceGo
  • Changed PLL1_PROP from 8 bit to 7 bit field in register map Go
  • Changed PLL1_PROP_FL from 8 bit to 7 bit field in register map Go
  • Changed PLL1_STORAGE_CELL 40 bit to 6 bit field. Not a 40 bit thermometer code. Set registers 0x66, 0x67, 0x68, 0x69 to RSRVD in register map Go
  • Changed PLL2_PROP from 8 bit to 6 bit field in register map Go
  • Changed PLL2_INTG from 8 bit to 5 bit field in register map Go
  • Added register 0xAC for field PLL1_TSTMODE_REF_FB_EN in register mapGo
  • Added register 0xAD for fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO in register mapGo
  • Added register 0xF6 for PLL2_DLD_EN in register mapGo
  • Deleted unused DEVID valuesGo
  • Changed reset value for CHIPID from 0x1 to 0x3Go
  • Changed reset value for CHIPVER from 0x1 to 0x1B Go
  • Changed PLL1_PROP from 8 bit to 7 bit field in register definition Go
  • Changed PLL1_PROP_FL from 8 bit to 7 bit field in register definition Go
  • Deleted 'PLL1 Start-up in Holdover.' text from the PLL1_STARTUP_HOLDOVER_EN bit descriptionGo
  • Changed PLL2_PROP field size from 8 bits to 6 bits in register definition Go
  • Changed PLL2_INTG field from 8 bit to 5 bit field in register 0x80 definitionGo
  • Added definition and requirement for setting PLL2_LD_WNDW_SIZE = 0 in register 0x85 definition Go
  • Added definition and requirement for setting PLL2_LD_WNDW_SIZE_INITIAL = 0 in register 0x86 definitionGo
  • Added note for using PLL1/2 REF/FB(SYS) status output for STAT0 Go
  • Added note for using PLL1/2 REF/FB(SYS) status output for STAT1 Go
  • Added note for using PLL1/2 REF/FB(SYS) status output for SYNC Go
  • Added register 0xAC to register description. New field PLL1_TSTMODE_REF_FB_EN.Go
  • Added register 0xAD to register description. New fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO.Go
  • Added register 0xF6 to register description. New field PLL2_DLD_ENGo
  • Added register 0xF7 to register description. New field PLL2_DUAL_LOOP_EN Go
  • Changed Channel 5 and 6 FBClock Buffers from: Low Skew to: Zero Delay ModeGo
  • Changed registers for WINDOW SIZE and LOCK COUNT. Updated equation to reflect the more general WINDOW SIZE and LOCK COUNT names and count frequency. Removed reference to holdover. Updated descriptive text Go
  • Updated minimum lock time calculation example to reflect updated register names and count frequency Go
  • Simplified HSDS format description Go

Changes from * Revision (January 2017) to A Revision

  • Removed the 16 differential output clock and 6 frequency group features from the LMK04610Go
  • Removed the 4 reference input feature from the LMK04610Go
  • Changed text from: –70-dBc PSRR to: –80dBc PSRR on VDDOGo
  • Changed SPI Interface default from: 3-wire to: 4-wire Go
  • Changed VCO frequency from: 5.8 to 6.2 GHz to: 5.8 to 6.175 GHzGo
  • Changed VCO frequency from: 6200 MHz to: 6175 MHzGo
  • Updated PLL1_CAP pin descriptionGo
  • Removed tablenote from the doubler input frequency parameterGo
  • Changed VCO tuning range maximum from: 6200 to: 6175Go
  • Changed tablenote text from: ATE tested at 2949.12 MHz to: ATE tested at 258 MHzGo
  • Removed the CLKin2/CLKin2*, and CLKin3/CLKin3* inputs from the LMK04610Go
  • Updated the Functional Block DiagramGo
  • Added content to the Driving CLKin and OSCin Pins With a Differential Source sectionGo
  • Changed text from: Either AC coupling or DC coupling may be used. to: The clock is internally AC-coupled.Go
  • Updated Figure 36Go
  • Changed the tuning range of the oscillator from: 6200 MHz to: 6175 MHzGo
  • Updated Figure 49Go
  • Changed the caption title on Figure 53Go
  • Changed the caption title on Figure 54Go
  • Changed the caption title on Figure 55Go