SNAS718C December   2016  – December 2017 LMK60E0-156M , LMK60E0-212M , LMK60E2-100M , LMK60E2-125M , LMK60E2-156M , LMK60I2-100M , LMK60I2-322M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Additional Reliability and Qualification
  7. Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Parameter Measurement Information

Device Output Configurations

LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M lvpecl_output_dc_configuration_snas687.gif Figure 1. LVPECL Output DC Configuration During Device Test
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M lvds_output_dc_configuration_snas687.gif Figure 2. LVDS Output DC Configuration During Device Test
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M hcsl_output_dc_configuration_snas687.gif Figure 3. HCSL Output DC Configuration During Device Test Also compatible with 85 Ω termination
Also compatible with 85 Ω termination
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M lvpecl_output_ac_configuration_snas687.gif Figure 4. LVPECL Output AC Configuration During Device Test
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M lvds_output_ac_configuration_snas687.gif Figure 5. LVDS Output AC Configuration During Device Test
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M hcsl_output_ac_configuration_snas687.gif Figure 6. HCSL Output AC Configuration During Device Test
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M psrr_test_setup_snas687.gif Figure 7. PSRR Test Setup
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M differential_output_voltage_rise_fall_time_snas674.gif Figure 8. Differential Output Voltage and Rise/Fall Time